fixup: Improve the aligment check

Author: djtodoro

llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp

@@ -142,6 +142,11 @@ bool RISCVLoadStoreOpt::tryToPairLdStInst(MachineBasicBlock::iterator &MBBI) {
   return false;
 }
 
+// Merge two adjacent load/store instructions into a paired instruction
+// (LDP/SDP/SWP/LWP) if the effective address is 16-byte aligned. This function
+// selects the appropriate paired opcode, verifies that the memory operand (or
+// fixed-stack slot) is 16-byte aligned, and checks that the offset is valid. If
+// all conditions are met, it builds and inserts the paired instruction.
 bool RISCVLoadStoreOpt::tryConvertToLdStPair(
     MachineBasicBlock::iterator First, MachineBasicBlock::iterator Second) {
   unsigned PairOpc;
@@ -166,16 +171,22 @@ bool RISCVLoadStoreOpt::tryConvertToLdStPair(
   MachineFunction *MF = First->getMF();
   const MachineMemOperand *MMO = *First->memoperands_begin();
   Align MMOAlign = MMO->getAlign();
-  if (const PseudoSourceValue *Source = MMO->getPseudoValue())
+
+  // The stack pointer shall be aligned to a 128-bit per ABI.
+  if (const PseudoSourceValue *Source = MMO->getPseudoValue()) {
     if (Source->kind() == PseudoSourceValue::FixedStack)
       MMOAlign = MF->getSubtarget().getFrameLowering()->getStackAlign();
+  }
 
-  if (MMOAlign < Align(MMO->getSize().getValue() * 2))
+  // Only pair if alignment is exactly 16 bytes.
+  if (MMOAlign != 16)
     return false;
+
   int64_t Offset = First->getOperand(2).getImm();
   if (!isUInt<7>(Offset) ||
       !isAligned(Align(MMO->getSize().getValue()), Offset))
     return false;
+
   MachineInstrBuilder MIB = BuildMI(
       *MF,
       First->getDebugLoc().get() ? First->getDebugLoc() : Second->getDebugLoc(),

llvm/test/CodeGen/RISCV/load-store-pair.ll

@@ -199,10 +199,8 @@ define dso_local void @testi(i8** nocapture noundef readonly %a) local_unnamed_a
 ; RV64I_PAIR-NEXT:    .cfi_offset s3, -16
 ; RV64I_PAIR-NEXT:    .cfi_offset s4, -24
 ; RV64I_PAIR-NEXT:    .cfi_offset s5, -32
-; RV64I_PAIR-NEXT:    ld s3, 0(a0)
-; RV64I_PAIR-NEXT:    ld s2, 8(a0)
-; RV64I_PAIR-NEXT:    ld s5, 16(a0)
-; RV64I_PAIR-NEXT:    ld s4, 24(a0)
+; RV64I_PAIR-NEXT:    mips.ldp s3, s2, 0(a0)
+; RV64I_PAIR-NEXT:    mips.ldp s5, s4, 16(a0)
 ; RV64I_PAIR-NEXT:    #APP
 ; RV64I_PAIR-NEXT:    #NO_APP
 ; RV64I_PAIR-NEXT:    mips.ldp s3, s2, 16(sp) # 16-byte Folded Reload
@@ -225,10 +223,8 @@ define dso_local void @testi(i8** nocapture noundef readonly %a) local_unnamed_a
 ; RV64P_8700-NEXT:    .cfi_offset s3, -16
 ; RV64P_8700-NEXT:    .cfi_offset s4, -24
 ; RV64P_8700-NEXT:    .cfi_offset s5, -32
-; RV64P_8700-NEXT:    ld s3, 0(a0)
-; RV64P_8700-NEXT:    ld s2, 8(a0)
-; RV64P_8700-NEXT:    ld s5, 16(a0)
-; RV64P_8700-NEXT:    ld s4, 24(a0)
+; RV64P_8700-NEXT:    mips.ldp s3, s2, 0(a0)
+; RV64P_8700-NEXT:    mips.ldp s5, s4, 16(a0)
 ; RV64P_8700-NEXT:    #APP
 ; RV64P_8700-NEXT:    #NO_APP
 ; RV64P_8700-NEXT:    mips.ldp s3, s2, 16(sp) # 16-byte Folded Reload
@@ -251,10 +247,8 @@ define dso_local void @testi(i8** nocapture noundef readonly %a) local_unnamed_a
 ; RV64D_PAIR-NEXT:    .cfi_offset s3, -16
 ; RV64D_PAIR-NEXT:    .cfi_offset s4, -24
 ; RV64D_PAIR-NEXT:    .cfi_offset s5, -32
-; RV64D_PAIR-NEXT:    ld s3, 0(a0)
-; RV64D_PAIR-NEXT:    ld s2, 8(a0)
-; RV64D_PAIR-NEXT:    ld s5, 16(a0)
-; RV64D_PAIR-NEXT:    ld s4, 24(a0)
+; RV64D_PAIR-NEXT:    mips.ldp s3, s2, 0(a0)
+; RV64D_PAIR-NEXT:    mips.ldp s5, s4, 16(a0)
 ; RV64D_PAIR-NEXT:    #APP
 ; RV64D_PAIR-NEXT:    #NO_APP
 ; RV64D_PAIR-NEXT:    mips.ldp s3, s2, 16(sp) # 16-byte Folded Reload
@@ -298,12 +292,12 @@ define dso_local void @testi(i8** nocapture noundef readonly %a) local_unnamed_a
 ; RV64D_NOPAIR-NEXT:    ret
 entry:
   %arrayidx = getelementptr inbounds i8*, i8** %a, i64 1
-  %0 = load i8*, i8** %arrayidx, align 8
-  %1 = load i8*, i8** %a, align 8
+  %0 = load i8*, i8** %arrayidx, align 16
+  %1 = load i8*, i8** %a, align 16
   %arrayidx2 = getelementptr inbounds i8*, i8** %a, i64 3
-  %2 = load i8*, i8** %arrayidx2, align 8
+  %2 = load i8*, i8** %arrayidx2, align 16
   %arrayidx3 = getelementptr inbounds i8*, i8** %a, i64 2
-  %3 = load i8*, i8** %arrayidx3, align 8
+  %3 = load i8*, i8** %arrayidx3, align 16
   tail call void asm sideeffect "", "{x18},{x19},{x20},{x21}"(i8* %0, i8* %1, i8* %2, i8* %3)
   ret void
 }