@@ -9342,7 +9342,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
93429342
93439343 // See if we can use a vector load to get all of the elements.
93449344 {
9345- SmallVector<SDValue, 64> Ops(Op->op_begin(), Op->op_begin() + NumElems);
9345+ SmallVector<SDValue, 64> Ops(Op->ops().take_front( NumElems) );
93469346 if (SDValue LD =
93479347 EltsFromConsecutiveLoads(VT, Ops, dl, DAG, Subtarget, false))
93489348 return LD;
@@ -23219,7 +23219,7 @@ static SDValue EmitTest(SDValue Op, X86::CondCode X86CC, const SDLoc &dl,
2321923219 DAG.getConstant(0, dl, Op.getValueType()));
2322023220 }
2322123221 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
23222- SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
23222+ SmallVector<SDValue, 4> Ops(Op->ops().take_front( NumOperands) );
2322323223
2322423224 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
2322523225 DAG.ReplaceAllUsesOfValueWith(SDValue(Op.getNode(), 0), New);
@@ -30377,7 +30377,7 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget &Subtarget,
3037730377 // element to the other.
3037830378 // This optimized lowering is only valid if the elements in a pair can
3037930379 // be treated identically.
30380- SmallVector<SDValue, 32> AmtWideElts(Amt->op_begin(), Amt->op_end ());
30380+ SmallVector<SDValue, 32> AmtWideElts(Amt->ops ());
3038130381 SmallVector<SDValue, 32> TmpAmtWideElts;
3038230382 int WideEltSizeInBits = EltSizeInBits;
3038330383 while (WideEltSizeInBits < 32) {
@@ -32908,7 +32908,7 @@ static SDValue ExtendToType(SDValue InOp, MVT NVT, SelectionDAG &DAG,
3290832908 EVT EltVT = InOp.getOperand(0).getValueType();
3290932909 SDValue FillVal =
3291032910 FillWithZeroes ? DAG.getConstant(0, dl, EltVT) : DAG.getUNDEF(EltVT);
32911- SmallVector<SDValue, 16> Ops(InOp->op_begin(), InOp->op_end ());
32911+ SmallVector<SDValue, 16> Ops(InOp->ops ());
3291232912 Ops.append(WidenNumElts - InNumElts, FillVal);
3291332913 return DAG.getBuildVector(NVT, dl, Ops);
3291432914 }
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