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[RISCV][GISel] Support libcalls for f32/f64 acos/asin/atan/atan2/cosh/sinh/tanh.
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4 files changed

+667
-18
lines changed

4 files changed

+667
-18
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -574,8 +574,10 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
574574
G_INTRINSIC_ROUNDEVEN})
575575
.libcallFor({s32, s64});
576576

577-
getActionDefinitionsBuilder(
578-
{G_FCOS, G_FSIN, G_FPOW, G_FLOG, G_FLOG2, G_FLOG10, G_FEXP, G_FEXP2, G_FEXP10})
577+
getActionDefinitionsBuilder({G_FCOS, G_FSIN, G_FTAN, G_FPOW, G_FLOG, G_FLOG2,
578+
G_FLOG10, G_FEXP, G_FEXP2, G_FEXP10, G_FACOS,
579+
G_FASIN, G_FATAN, G_FATAN2, G_FCOSH, G_FSINH,
580+
G_FTANH})
579581
.libcallFor({s32, s64});
580582

581583
getActionDefinitionsBuilder(G_VASTART).customFor({p0});

‎llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll‎

Lines changed: 319 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1021,3 +1021,322 @@ define i1 @isnan_d_fpclass(double %x) {
10211021
%1 = call i1 @llvm.is.fpclass.f64(double %x, i32 3) ; nan
10221022
ret i1 %1
10231023
}
1024+
1025+
define double @tan_f64(double %a) nounwind {
1026+
; RV32IFD-LABEL: tan_f64:
1027+
; RV32IFD: # %bb.0:
1028+
; RV32IFD-NEXT: addi sp, sp, -16
1029+
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1030+
; RV32IFD-NEXT: call tan
1031+
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1032+
; RV32IFD-NEXT: addi sp, sp, 16
1033+
; RV32IFD-NEXT: ret
1034+
;
1035+
; RV64IFD-LABEL: tan_f64:
1036+
; RV64IFD: # %bb.0:
1037+
; RV64IFD-NEXT: addi sp, sp, -16
1038+
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1039+
; RV64IFD-NEXT: call tan
1040+
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1041+
; RV64IFD-NEXT: addi sp, sp, 16
1042+
; RV64IFD-NEXT: ret
1043+
;
1044+
; RV32I-LABEL: tan_f64:
1045+
; RV32I: # %bb.0:
1046+
; RV32I-NEXT: addi sp, sp, -16
1047+
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1048+
; RV32I-NEXT: call tan
1049+
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1050+
; RV32I-NEXT: addi sp, sp, 16
1051+
; RV32I-NEXT: ret
1052+
;
1053+
; RV64I-LABEL: tan_f64:
1054+
; RV64I: # %bb.0:
1055+
; RV64I-NEXT: addi sp, sp, -16
1056+
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1057+
; RV64I-NEXT: call tan
1058+
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1059+
; RV64I-NEXT: addi sp, sp, 16
1060+
; RV64I-NEXT: ret
1061+
%1 = call double @llvm.tan.f64(double %a)
1062+
ret double %1
1063+
}
1064+
define double @asin_f64(double %a) nounwind {
1065+
; RV32IFD-LABEL: asin_f64:
1066+
; RV32IFD: # %bb.0:
1067+
; RV32IFD-NEXT: addi sp, sp, -16
1068+
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1069+
; RV32IFD-NEXT: call asin
1070+
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1071+
; RV32IFD-NEXT: addi sp, sp, 16
1072+
; RV32IFD-NEXT: ret
1073+
;
1074+
; RV64IFD-LABEL: asin_f64:
1075+
; RV64IFD: # %bb.0:
1076+
; RV64IFD-NEXT: addi sp, sp, -16
1077+
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1078+
; RV64IFD-NEXT: call asin
1079+
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1080+
; RV64IFD-NEXT: addi sp, sp, 16
1081+
; RV64IFD-NEXT: ret
1082+
;
1083+
; RV32I-LABEL: asin_f64:
1084+
; RV32I: # %bb.0:
1085+
; RV32I-NEXT: addi sp, sp, -16
1086+
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1087+
; RV32I-NEXT: call asin
1088+
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1089+
; RV32I-NEXT: addi sp, sp, 16
1090+
; RV32I-NEXT: ret
1091+
;
1092+
; RV64I-LABEL: asin_f64:
1093+
; RV64I: # %bb.0:
1094+
; RV64I-NEXT: addi sp, sp, -16
1095+
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1096+
; RV64I-NEXT: call asin
1097+
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1098+
; RV64I-NEXT: addi sp, sp, 16
1099+
; RV64I-NEXT: ret
1100+
%1 = call double @llvm.asin.f64(double %a)
1101+
ret double %1
1102+
}
1103+
1104+
define double @acos_f64(double %a) nounwind {
1105+
; RV32IFD-LABEL: acos_f64:
1106+
; RV32IFD: # %bb.0:
1107+
; RV32IFD-NEXT: addi sp, sp, -16
1108+
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1109+
; RV32IFD-NEXT: call acos
1110+
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1111+
; RV32IFD-NEXT: addi sp, sp, 16
1112+
; RV32IFD-NEXT: ret
1113+
;
1114+
; RV64IFD-LABEL: acos_f64:
1115+
; RV64IFD: # %bb.0:
1116+
; RV64IFD-NEXT: addi sp, sp, -16
1117+
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1118+
; RV64IFD-NEXT: call acos
1119+
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1120+
; RV64IFD-NEXT: addi sp, sp, 16
1121+
; RV64IFD-NEXT: ret
1122+
;
1123+
; RV32I-LABEL: acos_f64:
1124+
; RV32I: # %bb.0:
1125+
; RV32I-NEXT: addi sp, sp, -16
1126+
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1127+
; RV32I-NEXT: call acos
1128+
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1129+
; RV32I-NEXT: addi sp, sp, 16
1130+
; RV32I-NEXT: ret
1131+
;
1132+
; RV64I-LABEL: acos_f64:
1133+
; RV64I: # %bb.0:
1134+
; RV64I-NEXT: addi sp, sp, -16
1135+
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1136+
; RV64I-NEXT: call acos
1137+
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1138+
; RV64I-NEXT: addi sp, sp, 16
1139+
; RV64I-NEXT: ret
1140+
%1 = call double @llvm.acos.f64(double %a)
1141+
ret double %1
1142+
}
1143+
1144+
define double @atan_f64(double %a) nounwind {
1145+
; RV32IFD-LABEL: atan_f64:
1146+
; RV32IFD: # %bb.0:
1147+
; RV32IFD-NEXT: addi sp, sp, -16
1148+
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1149+
; RV32IFD-NEXT: call atan
1150+
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1151+
; RV32IFD-NEXT: addi sp, sp, 16
1152+
; RV32IFD-NEXT: ret
1153+
;
1154+
; RV64IFD-LABEL: atan_f64:
1155+
; RV64IFD: # %bb.0:
1156+
; RV64IFD-NEXT: addi sp, sp, -16
1157+
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1158+
; RV64IFD-NEXT: call atan
1159+
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1160+
; RV64IFD-NEXT: addi sp, sp, 16
1161+
; RV64IFD-NEXT: ret
1162+
;
1163+
; RV32I-LABEL: atan_f64:
1164+
; RV32I: # %bb.0:
1165+
; RV32I-NEXT: addi sp, sp, -16
1166+
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1167+
; RV32I-NEXT: call atan
1168+
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1169+
; RV32I-NEXT: addi sp, sp, 16
1170+
; RV32I-NEXT: ret
1171+
;
1172+
; RV64I-LABEL: atan_f64:
1173+
; RV64I: # %bb.0:
1174+
; RV64I-NEXT: addi sp, sp, -16
1175+
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1176+
; RV64I-NEXT: call atan
1177+
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1178+
; RV64I-NEXT: addi sp, sp, 16
1179+
; RV64I-NEXT: ret
1180+
%1 = call double @llvm.atan.f64(double %a)
1181+
ret double %1
1182+
}
1183+
1184+
define double @atan2_f64(double %a, double %b) nounwind {
1185+
; RV32IFD-LABEL: atan2_f64:
1186+
; RV32IFD: # %bb.0:
1187+
; RV32IFD-NEXT: addi sp, sp, -16
1188+
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1189+
; RV32IFD-NEXT: call atan2
1190+
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1191+
; RV32IFD-NEXT: addi sp, sp, 16
1192+
; RV32IFD-NEXT: ret
1193+
;
1194+
; RV64IFD-LABEL: atan2_f64:
1195+
; RV64IFD: # %bb.0:
1196+
; RV64IFD-NEXT: addi sp, sp, -16
1197+
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1198+
; RV64IFD-NEXT: call atan2
1199+
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1200+
; RV64IFD-NEXT: addi sp, sp, 16
1201+
; RV64IFD-NEXT: ret
1202+
;
1203+
; RV32I-LABEL: atan2_f64:
1204+
; RV32I: # %bb.0:
1205+
; RV32I-NEXT: addi sp, sp, -16
1206+
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1207+
; RV32I-NEXT: call atan2
1208+
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1209+
; RV32I-NEXT: addi sp, sp, 16
1210+
; RV32I-NEXT: ret
1211+
;
1212+
; RV64I-LABEL: atan2_f64:
1213+
; RV64I: # %bb.0:
1214+
; RV64I-NEXT: addi sp, sp, -16
1215+
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1216+
; RV64I-NEXT: call atan2
1217+
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1218+
; RV64I-NEXT: addi sp, sp, 16
1219+
; RV64I-NEXT: ret
1220+
%1 = call double @llvm.atan2.f64(double %a, double %b)
1221+
ret double %1
1222+
}
1223+
1224+
define double @sinh_f64(double %a) nounwind {
1225+
; RV32IFD-LABEL: sinh_f64:
1226+
; RV32IFD: # %bb.0:
1227+
; RV32IFD-NEXT: addi sp, sp, -16
1228+
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1229+
; RV32IFD-NEXT: call sinh
1230+
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1231+
; RV32IFD-NEXT: addi sp, sp, 16
1232+
; RV32IFD-NEXT: ret
1233+
;
1234+
; RV64IFD-LABEL: sinh_f64:
1235+
; RV64IFD: # %bb.0:
1236+
; RV64IFD-NEXT: addi sp, sp, -16
1237+
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1238+
; RV64IFD-NEXT: call sinh
1239+
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1240+
; RV64IFD-NEXT: addi sp, sp, 16
1241+
; RV64IFD-NEXT: ret
1242+
;
1243+
; RV32I-LABEL: sinh_f64:
1244+
; RV32I: # %bb.0:
1245+
; RV32I-NEXT: addi sp, sp, -16
1246+
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1247+
; RV32I-NEXT: call sinh
1248+
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1249+
; RV32I-NEXT: addi sp, sp, 16
1250+
; RV32I-NEXT: ret
1251+
;
1252+
; RV64I-LABEL: sinh_f64:
1253+
; RV64I: # %bb.0:
1254+
; RV64I-NEXT: addi sp, sp, -16
1255+
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1256+
; RV64I-NEXT: call sinh
1257+
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1258+
; RV64I-NEXT: addi sp, sp, 16
1259+
; RV64I-NEXT: ret
1260+
%1 = call double @llvm.sinh.f64(double %a)
1261+
ret double %1
1262+
}
1263+
1264+
define double @cosh_f64(double %a) nounwind {
1265+
; RV32IFD-LABEL: cosh_f64:
1266+
; RV32IFD: # %bb.0:
1267+
; RV32IFD-NEXT: addi sp, sp, -16
1268+
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1269+
; RV32IFD-NEXT: call cosh
1270+
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1271+
; RV32IFD-NEXT: addi sp, sp, 16
1272+
; RV32IFD-NEXT: ret
1273+
;
1274+
; RV64IFD-LABEL: cosh_f64:
1275+
; RV64IFD: # %bb.0:
1276+
; RV64IFD-NEXT: addi sp, sp, -16
1277+
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1278+
; RV64IFD-NEXT: call cosh
1279+
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1280+
; RV64IFD-NEXT: addi sp, sp, 16
1281+
; RV64IFD-NEXT: ret
1282+
;
1283+
; RV32I-LABEL: cosh_f64:
1284+
; RV32I: # %bb.0:
1285+
; RV32I-NEXT: addi sp, sp, -16
1286+
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1287+
; RV32I-NEXT: call cosh
1288+
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1289+
; RV32I-NEXT: addi sp, sp, 16
1290+
; RV32I-NEXT: ret
1291+
;
1292+
; RV64I-LABEL: cosh_f64:
1293+
; RV64I: # %bb.0:
1294+
; RV64I-NEXT: addi sp, sp, -16
1295+
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1296+
; RV64I-NEXT: call cosh
1297+
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1298+
; RV64I-NEXT: addi sp, sp, 16
1299+
; RV64I-NEXT: ret
1300+
%1 = call double @llvm.cosh.f64(double %a)
1301+
ret double %1
1302+
}
1303+
1304+
define double @tanh_f64(double %a) nounwind {
1305+
; RV32IFD-LABEL: tanh_f64:
1306+
; RV32IFD: # %bb.0:
1307+
; RV32IFD-NEXT: addi sp, sp, -16
1308+
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1309+
; RV32IFD-NEXT: call tanh
1310+
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1311+
; RV32IFD-NEXT: addi sp, sp, 16
1312+
; RV32IFD-NEXT: ret
1313+
;
1314+
; RV64IFD-LABEL: tanh_f64:
1315+
; RV64IFD: # %bb.0:
1316+
; RV64IFD-NEXT: addi sp, sp, -16
1317+
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1318+
; RV64IFD-NEXT: call tanh
1319+
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1320+
; RV64IFD-NEXT: addi sp, sp, 16
1321+
; RV64IFD-NEXT: ret
1322+
;
1323+
; RV32I-LABEL: tanh_f64:
1324+
; RV32I: # %bb.0:
1325+
; RV32I-NEXT: addi sp, sp, -16
1326+
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1327+
; RV32I-NEXT: call tanh
1328+
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1329+
; RV32I-NEXT: addi sp, sp, 16
1330+
; RV32I-NEXT: ret
1331+
;
1332+
; RV64I-LABEL: tanh_f64:
1333+
; RV64I: # %bb.0:
1334+
; RV64I-NEXT: addi sp, sp, -16
1335+
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1336+
; RV64I-NEXT: call tanh
1337+
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1338+
; RV64I-NEXT: addi sp, sp, 16
1339+
; RV64I-NEXT: ret
1340+
%1 = call double @llvm.tanh.f64(double %a)
1341+
ret double %1
1342+
}

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