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[AVR] Remove some custom decoder functions (NFCI) (#156852)
The generated decoding functions look identical to the custom ones, we only need to provide custom decoders for some operands.
1 parent 5a0d703 commit 1793fa8

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3 files changed

+19
-120
lines changed

3 files changed

+19
-120
lines changed

‎llvm/lib/Target/AVR/AVRInstrFormats.td‎

Lines changed: 3 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -128,8 +128,6 @@ class FRd<bits<4> opcode, bits<7> f, dag outs, dag ins, string asmstr,
128128
let Inst{11 - 9} = f{6 - 4};
129129
let Inst{8 - 4} = rd;
130130
let Inst{3 - 0} = f{3 - 0};
131-
132-
let DecoderMethod = "decodeFRd";
133131
}
134132

135133
//===----------------------------------------------------------------------===//
@@ -308,8 +306,6 @@ class FIORdA<dag outs, dag ins, string asmstr, list<dag> pattern>
308306
let Inst{10 - 9} = A{5 - 4};
309307
let Inst{8 - 4} = rd;
310308
let Inst{3 - 0} = A{3 - 0};
311-
312-
let DecoderMethod = "decodeFIORdA";
313309
}
314310

315311
//===----------------------------------------------------------------------===//
@@ -327,8 +323,6 @@ class FIOARr<dag outs, dag ins, string asmstr, list<dag> pattern>
327323
let Inst{10 - 9} = A{5 - 4};
328324
let Inst{8 - 4} = rr;
329325
let Inst{3 - 0} = A{3 - 0};
330-
331-
let DecoderMethod = "decodeFIOARr";
332326
}
333327

334328
//===----------------------------------------------------------------------===//
@@ -343,17 +337,10 @@ class FIOBIT<bits<2> t, dag outs, dag ins, string asmstr, list<dag> pattern>
343337
bits<5> addr;
344338
bits<3> b;
345339

346-
let Inst{15 - 12} = 0b1001;
347-
348-
let Inst{11 - 10} = 0b10;
340+
let Inst{15 - 10} = 0b100110;
349341
let Inst{9 - 8} = t;
350-
351-
let Inst{7 - 4} = addr{4 - 1};
352-
353-
let Inst{3} = addr{0};
342+
let Inst{7 - 3} = addr;
354343
let Inst{2 - 0} = b{2 - 0};
355-
356-
let DecoderMethod = "decodeFIOBIT";
357344
}
358345

359346
//===----------------------------------------------------------------------===//
@@ -412,8 +399,6 @@ class FBRsk<bit f, bits<3> s, dag outs, dag ins, string asmstr,
412399
let Inst{10} = f;
413400
let Inst{9 - 3} = k;
414401
let Inst{2 - 0} = s;
415-
416-
let DecoderMethod = "decodeCondBranch";
417402
}
418403

419404
//===----------------------------------------------------------------------===//
@@ -437,8 +422,6 @@ class FBRk<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
437422
let Inst{15 - 13} = 0b110;
438423
let Inst{12} = f;
439424
let Inst{11 - 0} = k;
440-
441-
let DecoderMethod = "decodeFBRk";
442425
}
443426

444427
//===----------------------------------------------------------------------===//
@@ -532,14 +515,8 @@ class FSK<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
532515

533516
let Inst{11} = 0;
534517
let Inst{10} = f;
535-
let Inst{9 - 8} = k{6 - 5};
536-
537-
let Inst{7 - 4} = k{4 - 1};
538-
539-
let Inst{3} = k{0};
518+
let Inst{9 - 3} = k;
540519
let Inst{2 - 0} = s;
541-
542-
let DecoderMethod = "decodeCondBranch";
543520
}
544521

545522
class ExtensionPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>

‎llvm/lib/Target/AVR/AVRInstrInfo.td‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -204,16 +204,19 @@ def memspi : Operand<iPTR> {
204204
def relbrtarget_7 : Operand<OtherVT> {
205205
let PrintMethod = "printPCRelImm";
206206
let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_7_pcrel>";
207+
let DecoderMethod = "decodeRelCondBrTarget7";
207208
}
208209

209210
def brtarget_13 : Operand<OtherVT> {
210211
let PrintMethod = "printPCRelImm";
211212
let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_13_pcrel>";
213+
let DecoderMethod = "decodeRelCondBrTarget13";
212214
}
213215

214216
def rcalltarget_13 : Operand<i16> {
215217
let PrintMethod = "printPCRelImm";
216218
let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_13_pcrel>";
219+
let DecoderMethod = "decodeRelCondBrTarget13";
217220
}
218221

219222
// The target of a 22 or 16-bit call/jmp instruction.

‎llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp‎

Lines changed: 13 additions & 94 deletions
Original file line numberDiff line numberDiff line change
@@ -97,41 +97,6 @@ static DecodeStatus DecodeZREGRegisterClass(MCInst &Inst,
9797
return MCDisassembler::Success;
9898
}
9999

100-
static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
101-
const MCDisassembler *Decoder) {
102-
unsigned addr = 0;
103-
addr |= fieldFromInstruction(Insn, 0, 4);
104-
addr |= fieldFromInstruction(Insn, 9, 2) << 4;
105-
unsigned reg = fieldFromInstruction(Insn, 4, 5);
106-
Inst.addOperand(MCOperand::createImm(addr));
107-
if (DecodeGPR8RegisterClass(Inst, reg, Address, Decoder) ==
108-
MCDisassembler::Fail)
109-
return MCDisassembler::Fail;
110-
return MCDisassembler::Success;
111-
}
112-
113-
static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address,
114-
const MCDisassembler *Decoder) {
115-
unsigned addr = 0;
116-
addr |= fieldFromInstruction(Insn, 0, 4);
117-
addr |= fieldFromInstruction(Insn, 9, 2) << 4;
118-
unsigned reg = fieldFromInstruction(Insn, 4, 5);
119-
if (DecodeGPR8RegisterClass(Inst, reg, Address, Decoder) ==
120-
MCDisassembler::Fail)
121-
return MCDisassembler::Fail;
122-
Inst.addOperand(MCOperand::createImm(addr));
123-
return MCDisassembler::Success;
124-
}
125-
126-
static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address,
127-
const MCDisassembler *Decoder) {
128-
unsigned addr = fieldFromInstruction(Insn, 3, 5);
129-
unsigned b = fieldFromInstruction(Insn, 0, 3);
130-
Inst.addOperand(MCOperand::createImm(addr));
131-
Inst.addOperand(MCOperand::createImm(b));
132-
return MCDisassembler::Success;
133-
}
134-
135100
static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Field,
136101
uint64_t Address,
137102
const MCDisassembler *Decoder) {
@@ -141,12 +106,19 @@ static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Field,
141106
return MCDisassembler::Success;
142107
}
143108

144-
static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address,
145-
const MCDisassembler *Decoder) {
146-
unsigned d = fieldFromInstruction(Insn, 4, 5);
147-
if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
148-
MCDisassembler::Fail)
149-
return MCDisassembler::Fail;
109+
static DecodeStatus decodeRelCondBrTarget7(MCInst &Inst, unsigned Field,
110+
uint64_t Address,
111+
const MCDisassembler *Decoder) {
112+
// The legal range is [-128, 126] (in bytes).
113+
Inst.addOperand(MCOperand::createImm(SignExtend32(Field, 7) << 1));
114+
return MCDisassembler::Success;
115+
}
116+
117+
static DecodeStatus decodeRelCondBrTarget13(MCInst &Inst, unsigned Field,
118+
uint64_t Address,
119+
const MCDisassembler *Decoder) {
120+
// The legal range is [-4096, 4094] (in bytes).
121+
Inst.addOperand(MCOperand::createImm(SignExtend32(Field, 12) << 1));
150122
return MCDisassembler::Success;
151123
}
152124

@@ -225,59 +197,6 @@ static DecodeStatus decodeMemri(MCInst &Inst, unsigned Insn, uint64_t Address,
225197
return MCDisassembler::Success;
226198
}
227199

228-
static DecodeStatus decodeFBRk(MCInst &Inst, unsigned Insn, uint64_t Address,
229-
const MCDisassembler *Decoder) {
230-
// Decode the opcode.
231-
switch (Insn & 0xf000) {
232-
case 0xc000:
233-
Inst.setOpcode(AVR::RJMPk);
234-
break;
235-
case 0xd000:
236-
Inst.setOpcode(AVR::RCALLk);
237-
break;
238-
default: // Unknown relative branch instruction.
239-
return MCDisassembler::Fail;
240-
}
241-
// Decode the relative offset.
242-
int16_t Offset = ((int16_t)((Insn & 0xfff) << 4)) >> 3;
243-
Inst.addOperand(MCOperand::createImm(Offset));
244-
return MCDisassembler::Success;
245-
}
246-
247-
static DecodeStatus decodeCondBranch(MCInst &Inst, unsigned Insn,
248-
uint64_t Address,
249-
const MCDisassembler *Decoder) {
250-
// These 8 instructions are not defined as aliases of BRBS/BRBC.
251-
DenseMap<unsigned, unsigned> brInsts = {
252-
{0x000, AVR::BRLOk}, {0x400, AVR::BRSHk}, {0x001, AVR::BREQk},
253-
{0x401, AVR::BRNEk}, {0x002, AVR::BRMIk}, {0x402, AVR::BRPLk},
254-
{0x004, AVR::BRLTk}, {0x404, AVR::BRGEk}};
255-
256-
// Get the relative offset.
257-
int16_t Offset = ((int16_t)((Insn & 0x3f8) << 6)) >> 8;
258-
259-
// Search the instruction pattern.
260-
auto NotAlias = [&Insn](const std::pair<unsigned, unsigned> &I) {
261-
return (Insn & 0x407) != I.first;
262-
};
263-
llvm::partition(brInsts, NotAlias);
264-
auto It = llvm::partition_point(brInsts, NotAlias);
265-
266-
// Decode the instruction.
267-
if (It != brInsts.end()) {
268-
// This instruction is not an alias of BRBC/BRBS.
269-
Inst.setOpcode(It->second);
270-
Inst.addOperand(MCOperand::createImm(Offset));
271-
} else {
272-
// Fall back to an ordinary BRBS/BRBC.
273-
Inst.setOpcode(Insn & 0x400 ? AVR::BRBCsk : AVR::BRBSsk);
274-
Inst.addOperand(MCOperand::createImm(Insn & 7));
275-
Inst.addOperand(MCOperand::createImm(Offset));
276-
}
277-
278-
return MCDisassembler::Success;
279-
}
280-
281200
static DecodeStatus decodeLoadStore(MCInst &Inst, unsigned Insn,
282201
uint64_t Address,
283202
const MCDisassembler *Decoder) {

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