address comment

Author: diggerlin

llvm/include/llvm/IR/IntrinsicsPowerPC.td

@@ -1837,16 +1837,16 @@ let TargetPrefix = "ppc" in {
                               Intrinsic<[],[],[]>;
   def int_ppc_lbarx :
     Intrinsic<[llvm_i32_ty], [llvm_ptr_ty],
-              [IntrReadMem, IntrArgMemOnly, IntrNoDuplicate]>;
+              [IntrReadMem, IntrArgMemOnly]>;
   def int_ppc_lharx :
     Intrinsic<[llvm_i32_ty],[llvm_ptr_ty],
-              [IntrReadMem, IntrArgMemOnly, IntrNoDuplicate]>;
+              [IntrReadMem, IntrArgMemOnly]>;
   def int_ppc_lwarx :
     Intrinsic<[llvm_i32_ty], [llvm_ptr_ty],
-              [IntrReadMem, IntrArgMemOnly, IntrNoDuplicate]>;
+              [IntrReadMem, IntrArgMemOnly]>;
   def int_ppc_ldarx :
     Intrinsic<[llvm_i64_ty],[llvm_ptr_ty],
-              [IntrReadMem, IntrArgMemOnly, IntrNoDuplicate]>;
+              [IntrReadMem, IntrArgMemOnly]>;
 
   def int_ppc_stdcx :
     ClangBuiltin<"__builtin_ppc_stdcx">,

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

@@ -1475,10 +1475,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
   setMinimumJumpTableEntries(PPCMinimumJumpTableEntries);
 
   setMinFunctionAlignment(Align(4));
-  if (Subtarget.hasPartwordAtomics())
-    setMinCmpXchgSizeInBits(8);
-  else
-    setMinCmpXchgSizeInBits(32);
+  setMinCmpXchgSizeInBits(Subtarget.hasPartwordAtomics() ? 8 : 32);
 
   switch (Subtarget.getCPUDirective()) {
   default: break;
@@ -12739,12 +12736,12 @@ Value *PPCTargetLowering::emitStoreConditional(IRBuilderBase &Builder,
   }
 
   if (SZ == 8 || SZ == 16)
-    Val = Builder.CreateZExt(Val, Builder.getIntNTy(32));;
+    Val = Builder.CreateZExt(Val, Builder.getInt32Ty());
+  ;
 
   Value *Call = Builder.CreateIntrinsic(IntID, {Addr, Val},
                                         /*FMFSource=*/nullptr, "stcx");
-  Value *Not = Builder.CreateXor(Call,Builder.getInt32(1));
-  return Not;
+  return Builder.CreateXor(Call, Builder.getInt32(1));
 }
 
 // The mappings for emitLeading/TrailingFence is taken from