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[LV] Add target-independent test for type-mismatch
The test suite of LoopVectorize suffers from a coverage hole when types mismatch, in the target-independent case. There is already interleave-allocsize-not-equal-typesize.ll under the AArch64 target written for the purposes of fixing specific bugs, but nothing exercising this in a target-independent fashion. Fix this by adapting a test from LoopAccessAnalysis' depend_diff_types.ll, and demonstrate that LoopVectorize only ever interleaves when types mismatch.
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‎llvm/test/Transforms/LoopVectorize/type-mismatch-interleave.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -passes=loop-vectorize -force-vector-width=4 -S %s | FileCheck %s
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; Tests demonstrating that LV only ever interleaves when types mismatch.
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define void @different_types(ptr noalias %src.1, ptr noalias %src.2, ptr noalias %dst.1, ptr noalias %dst.2, i64 %n) {
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; CHECK-LABEL: define void @different_types(
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; CHECK-SAME: ptr noalias [[SRC_1:%.*]], ptr noalias [[SRC_2:%.*]], ptr noalias [[DST_1:%.*]], ptr noalias [[DST_2:%.*]], i64 [[N:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1)
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX]], 4
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX]], 4
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[UMAX]], [[N_MOD_VF]]
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
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; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1
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; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2
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; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[SRC_1]], i64 [[TMP0]]
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; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[TMP4]], i32 0
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP5]], align 4
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; CHECK-NEXT: [[TMP6:%.*]] = trunc <4 x i64> [[WIDE_LOAD]] to <4 x i32>
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i64, ptr [[SRC_2]], i64 [[TMP0]]
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; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[TMP7]], i32 0
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; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i64>, ptr [[TMP8]], align 4
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; CHECK-NEXT: [[TMP9:%.*]] = add <4 x i64> [[WIDE_LOAD]], [[WIDE_LOAD1]]
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; CHECK-NEXT: [[TMP10:%.*]] = getelementptr nusw i64, ptr [[DST_1]], i64 [[TMP0]]
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; CHECK-NEXT: [[TMP11:%.*]] = getelementptr nusw i64, ptr [[DST_1]], i64 [[TMP1]]
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; CHECK-NEXT: [[TMP12:%.*]] = getelementptr nusw i64, ptr [[DST_1]], i64 [[TMP2]]
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; CHECK-NEXT: [[TMP13:%.*]] = getelementptr nusw i64, ptr [[DST_1]], i64 [[TMP3]]
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; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x i32> [[TMP6]], i32 0
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; CHECK-NEXT: store i32 [[TMP14]], ptr [[TMP10]], align 4
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; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x i32> [[TMP6]], i32 1
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; CHECK-NEXT: store i32 [[TMP15]], ptr [[TMP11]], align 4
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; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x i32> [[TMP6]], i32 2
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; CHECK-NEXT: store i32 [[TMP16]], ptr [[TMP12]], align 4
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; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i32> [[TMP6]], i32 3
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; CHECK-NEXT: store i32 [[TMP17]], ptr [[TMP13]], align 4
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; CHECK-NEXT: [[TMP18:%.*]] = getelementptr nusw i64, ptr [[DST_2]], i64 [[TMP0]]
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; CHECK-NEXT: [[TMP19:%.*]] = getelementptr nusw i64, ptr [[TMP18]], i32 0
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; CHECK-NEXT: store <4 x i64> [[TMP9]], ptr [[TMP19]], align 4
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
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; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[GEP_SRC_1:%.*]] = getelementptr i64, ptr [[SRC_1]], i64 [[IV]]
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; CHECK-NEXT: [[LD_SRC_1:%.*]] = load i64, ptr [[GEP_SRC_1]], align 4
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; CHECK-NEXT: [[LD_SRC_1_I32:%.*]] = trunc i64 [[LD_SRC_1]] to i32
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; CHECK-NEXT: [[GEP_SRC_2:%.*]] = getelementptr i64, ptr [[SRC_2]], i64 [[IV]]
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; CHECK-NEXT: [[LD_SRC_2:%.*]] = load i64, ptr [[GEP_SRC_2]], align 4
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; CHECK-NEXT: [[ADD:%.*]] = add i64 [[LD_SRC_1]], [[LD_SRC_2]]
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; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr nusw i64, ptr [[DST_1]], i64 [[IV]]
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; CHECK-NEXT: store i32 [[LD_SRC_1_I32]], ptr [[GEP_DST_1]], align 4
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; CHECK-NEXT: [[GEP_DST_2:%.*]] = getelementptr nusw i64, ptr [[DST_2]], i64 [[IV]]
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; CHECK-NEXT: store i64 [[ADD]], ptr [[GEP_DST_2]], align 4
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[COND:%.*]] = icmp ult i64 [[IV_NEXT]], [[N]]
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; CHECK-NEXT: br i1 [[COND]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%gep.src.1 = getelementptr i64, ptr %src.1, i64 %iv
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%ld.src.1 = load i64, ptr %gep.src.1
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%ld.src.1.i32 = trunc i64 %ld.src.1 to i32
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%gep.src.2 = getelementptr i64, ptr %src.2, i64 %iv
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%ld.src.2 = load i64, ptr %gep.src.2
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%add = add i64 %ld.src.1, %ld.src.2
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%gep.dst.1 = getelementptr nusw i64, ptr %dst.1, i64 %iv
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store i32 %ld.src.1.i32, ptr %gep.dst.1
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%gep.dst.2 = getelementptr nusw i64, ptr %dst.2, i64 %iv
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store i64 %add, ptr %gep.dst.2
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%iv.next = add nuw nsw i64 %iv, 1
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%cond = icmp ult i64 %iv.next, %n
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br i1 %cond, label %loop, label %exit
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exit:
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ret void
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}
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define void @different_types_rt_memcheck(ptr %src.1, ptr %src.2, ptr %dst.1, ptr %dst.2, i64 %n) {
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; CHECK-LABEL: define void @different_types_rt_memcheck(
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; CHECK-SAME: ptr [[SRC_1:%.*]], ptr [[SRC_2:%.*]], ptr [[DST_1:%.*]], ptr [[DST_2:%.*]], i64 [[N:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[SRC_25:%.*]] = ptrtoint ptr [[SRC_2]] to i64
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; CHECK-NEXT: [[SRC_13:%.*]] = ptrtoint ptr [[SRC_1]] to i64
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; CHECK-NEXT: [[DST_12:%.*]] = ptrtoint ptr [[DST_1]] to i64
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; CHECK-NEXT: [[DST_21:%.*]] = ptrtoint ptr [[DST_2]] to i64
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; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1)
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX]], 4
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
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; CHECK: [[VECTOR_MEMCHECK]]:
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; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[DST_21]], [[DST_12]]
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; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], 32
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; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[DST_12]], [[SRC_13]]
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; CHECK-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP1]], 32
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; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
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; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[DST_12]], [[SRC_25]]
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; CHECK-NEXT: [[DIFF_CHECK6:%.*]] = icmp ult i64 [[TMP2]], 32
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; CHECK-NEXT: [[CONFLICT_RDX7:%.*]] = or i1 [[CONFLICT_RDX]], [[DIFF_CHECK6]]
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; CHECK-NEXT: [[TMP3:%.*]] = sub i64 [[DST_21]], [[SRC_13]]
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; CHECK-NEXT: [[DIFF_CHECK8:%.*]] = icmp ult i64 [[TMP3]], 32
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; CHECK-NEXT: [[CONFLICT_RDX9:%.*]] = or i1 [[CONFLICT_RDX7]], [[DIFF_CHECK8]]
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; CHECK-NEXT: [[TMP4:%.*]] = sub i64 [[DST_21]], [[SRC_25]]
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; CHECK-NEXT: [[DIFF_CHECK10:%.*]] = icmp ult i64 [[TMP4]], 32
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; CHECK-NEXT: [[CONFLICT_RDX11:%.*]] = or i1 [[CONFLICT_RDX9]], [[DIFF_CHECK10]]
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; CHECK-NEXT: br i1 [[CONFLICT_RDX11]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX]], 4
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[UMAX]], [[N_MOD_VF]]
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 0
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; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 1
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; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 2
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; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 3
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; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[SRC_1]], i64 [[TMP5]]
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; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i64, ptr [[TMP9]], i32 0
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP10]], align 4
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; CHECK-NEXT: [[TMP11:%.*]] = trunc <4 x i64> [[WIDE_LOAD]] to <4 x i32>
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; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i64, ptr [[SRC_2]], i64 [[TMP5]]
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; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i64, ptr [[TMP12]], i32 0
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; CHECK-NEXT: [[WIDE_LOAD12:%.*]] = load <4 x i64>, ptr [[TMP13]], align 4
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; CHECK-NEXT: [[TMP14:%.*]] = add <4 x i64> [[WIDE_LOAD]], [[WIDE_LOAD12]]
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; CHECK-NEXT: [[TMP15:%.*]] = getelementptr nusw i64, ptr [[DST_1]], i64 [[TMP5]]
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; CHECK-NEXT: [[TMP16:%.*]] = getelementptr nusw i64, ptr [[DST_1]], i64 [[TMP6]]
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; CHECK-NEXT: [[TMP17:%.*]] = getelementptr nusw i64, ptr [[DST_1]], i64 [[TMP7]]
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; CHECK-NEXT: [[TMP18:%.*]] = getelementptr nusw i64, ptr [[DST_1]], i64 [[TMP8]]
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; CHECK-NEXT: [[TMP19:%.*]] = extractelement <4 x i32> [[TMP11]], i32 0
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; CHECK-NEXT: store i32 [[TMP19]], ptr [[TMP15]], align 4
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; CHECK-NEXT: [[TMP20:%.*]] = extractelement <4 x i32> [[TMP11]], i32 1
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; CHECK-NEXT: store i32 [[TMP20]], ptr [[TMP16]], align 4
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; CHECK-NEXT: [[TMP21:%.*]] = extractelement <4 x i32> [[TMP11]], i32 2
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; CHECK-NEXT: store i32 [[TMP21]], ptr [[TMP17]], align 4
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; CHECK-NEXT: [[TMP22:%.*]] = extractelement <4 x i32> [[TMP11]], i32 3
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; CHECK-NEXT: store i32 [[TMP22]], ptr [[TMP18]], align 4
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; CHECK-NEXT: [[TMP23:%.*]] = getelementptr nusw i64, ptr [[DST_2]], i64 [[TMP5]]
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; CHECK-NEXT: [[TMP24:%.*]] = getelementptr nusw i64, ptr [[TMP23]], i32 0
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; CHECK-NEXT: store <4 x i64> [[TMP14]], ptr [[TMP24]], align 4
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
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; CHECK-NEXT: [[TMP25:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP25]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[GEP_SRC_1:%.*]] = getelementptr i64, ptr [[SRC_1]], i64 [[IV]]
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; CHECK-NEXT: [[LD_SRC_1:%.*]] = load i64, ptr [[GEP_SRC_1]], align 4
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; CHECK-NEXT: [[LD_SRC_1_I32:%.*]] = trunc i64 [[LD_SRC_1]] to i32
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; CHECK-NEXT: [[GEP_SRC_2:%.*]] = getelementptr i64, ptr [[SRC_2]], i64 [[IV]]
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; CHECK-NEXT: [[LD_SRC_2:%.*]] = load i64, ptr [[GEP_SRC_2]], align 4
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; CHECK-NEXT: [[ADD:%.*]] = add i64 [[LD_SRC_1]], [[LD_SRC_2]]
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; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr nusw i64, ptr [[DST_1]], i64 [[IV]]
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; CHECK-NEXT: store i32 [[LD_SRC_1_I32]], ptr [[GEP_DST_1]], align 4
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; CHECK-NEXT: [[GEP_DST_2:%.*]] = getelementptr nusw i64, ptr [[DST_2]], i64 [[IV]]
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; CHECK-NEXT: store i64 [[ADD]], ptr [[GEP_DST_2]], align 4
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[COND:%.*]] = icmp ult i64 [[IV_NEXT]], [[N]]
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; CHECK-NEXT: br i1 [[COND]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP5:![0-9]+]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%gep.src.1 = getelementptr i64, ptr %src.1, i64 %iv
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%ld.src.1 = load i64, ptr %gep.src.1
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%ld.src.1.i32 = trunc i64 %ld.src.1 to i32
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%gep.src.2 = getelementptr i64, ptr %src.2, i64 %iv
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%ld.src.2 = load i64, ptr %gep.src.2
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%add = add i64 %ld.src.1, %ld.src.2
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%gep.dst.1 = getelementptr nusw i64, ptr %dst.1, i64 %iv
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store i32 %ld.src.1.i32, ptr %gep.dst.1
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%gep.dst.2 = getelementptr nusw i64, ptr %dst.2, i64 %iv
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store i64 %add, ptr %gep.dst.2
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%iv.next = add nuw nsw i64 %iv, 1
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%cond = icmp ult i64 %iv.next, %n
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br i1 %cond, label %loop, label %exit
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exit:
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ret void
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}
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;.
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; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
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; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
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; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
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; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
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; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
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; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]}
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;.

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