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[CodeGen][NVPTX][WebAssembly] Add copyReg interface to TargetInstrInfo that takes Register instead of MCRegister.
NVPTX, SPIRV, and WebAssembly all need to expand copies of virtual registers because they don't go through register allocation. The copyPhysReg interface currently used takes two MCRegister arguments that get implicitly converted from Registers in LowerCopy. It should be illegal to convert a virtual register Register to an MCRegister. This patch adds a new interface copyReg that takes two Registers. The default implementation falls back to copyPhysReg with an explicit conversion. NVPTX, SPIRV, and WebAssembly are modified to implement the new interface. I chose this approach to be least disruptive to out of tree targets. Alternatively, we could change copyPhysReg to take Register operands, though we would probably want to rename it to remove "Phys".
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8 files changed

+41
-33
lines changed

8 files changed

+41
-33
lines changed

‎llvm/include/llvm/CodeGen/TargetInstrInfo.h‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1040,6 +1040,16 @@ class TargetInstrInfo : public MCInstrInfo {
10401040
bool RenamableSrc = false) const {
10411041
llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
10421042
}
1043+
// Similar to copycopyPhysReg, but for targets that don't do register
1044+
// allocation and need to copy virtual registers like NVPTX, SPIR-V, and
1045+
// WebAssembly.
1046+
virtual void copyReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1047+
const DebugLoc &DL, Register DestReg, Register SrcReg,
1048+
bool KillSrc, bool RenamableDest = false,
1049+
bool RenamableSrc = false) const {
1050+
copyPhysReg(MBB, MI, DL, DestReg.asMCReg(), SrcReg.asMCReg(), KillSrc,
1051+
RenamableDest, RenamableSrc);
1052+
}
10431053

10441054
/// Allow targets to tell MachineVerifier whether a specific register
10451055
/// MachineOperand can be used as part of PC-relative addressing.

‎llvm/lib/CodeGen/TargetInstrInfo.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -822,10 +822,10 @@ void TargetInstrInfo::lowerCopy(MachineInstr *MI,
822822
return;
823823
}
824824

825-
copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(), DstMO.getReg(),
826-
SrcMO.getReg(), SrcMO.isKill(),
827-
DstMO.getReg().isPhysical() ? DstMO.isRenamable() : false,
828-
SrcMO.getReg().isPhysical() ? SrcMO.isRenamable() : false);
825+
copyReg(*MI->getParent(), MI, MI->getDebugLoc(), DstMO.getReg(),
826+
SrcMO.getReg(), SrcMO.isKill(),
827+
DstMO.getReg().isPhysical() ? DstMO.isRenamable() : false,
828+
SrcMO.getReg().isPhysical() ? SrcMO.isRenamable() : false);
829829

830830
if (MI->getNumOperands() > 2)
831831
transferImplicitOperands(MI, TRI);

‎llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -26,11 +26,10 @@ void NVPTXInstrInfo::anchor() {}
2626

2727
NVPTXInstrInfo::NVPTXInstrInfo() : RegInfo() {}
2828

29-
void NVPTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
30-
MachineBasicBlock::iterator I,
31-
const DebugLoc &DL, MCRegister DestReg,
32-
MCRegister SrcReg, bool KillSrc,
33-
bool RenamableDest, bool RenamableSrc) const {
29+
void NVPTXInstrInfo::copyReg(MachineBasicBlock &MBB,
30+
MachineBasicBlock::iterator I, const DebugLoc &DL,
31+
Register DestReg, Register SrcReg, bool KillSrc,
32+
bool RenamableDest, bool RenamableSrc) const {
3433
const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3534
const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
3635
const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);

‎llvm/lib/Target/NVPTX/NVPTXInstrInfo.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -50,10 +50,10 @@ class NVPTXInstrInfo : public NVPTXGenInstrInfo {
5050
* MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const;
5151
*/
5252

53-
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
54-
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
55-
bool KillSrc, bool RenamableDest = false,
56-
bool RenamableSrc = false) const override;
53+
void copyReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
54+
const DebugLoc &DL, Register DestReg, Register SrcReg,
55+
bool KillSrc, bool RenamableDest = false,
56+
bool RenamableSrc = false) const override;
5757

5858
// Branch analysis.
5959
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,

‎llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -256,11 +256,10 @@ unsigned SPIRVInstrInfo::insertBranch(MachineBasicBlock &MBB,
256256
return 1;
257257
}
258258

259-
void SPIRVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
260-
MachineBasicBlock::iterator I,
261-
const DebugLoc &DL, MCRegister DestReg,
262-
MCRegister SrcReg, bool KillSrc,
263-
bool RenamableDest, bool RenamableSrc) const {
259+
void SPIRVInstrInfo::copyReg(MachineBasicBlock &MBB,
260+
MachineBasicBlock::iterator I, const DebugLoc &DL,
261+
Register DestReg, Register SrcReg, bool KillSrc,
262+
bool RenamableDest, bool RenamableSrc) const {
264263
// Actually we don't need this COPY instruction. However if we do nothing with
265264
// it, post RA pseudo instrs expansion just removes it and we get the code
266265
// with undef registers. Therefore, we need to replace all uses of dst with

‎llvm/lib/Target/SPIRV/SPIRVInstrInfo.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -50,10 +50,10 @@ class SPIRVInstrInfo : public SPIRVGenInstrInfo {
5050
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
5151
const DebugLoc &DL,
5252
int *BytesAdded = nullptr) const override;
53-
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
54-
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
55-
bool KillSrc, bool RenamableDest = false,
56-
bool RenamableSrc = false) const override;
53+
void copyReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
54+
const DebugLoc &DL, Register DestReg, Register SrcReg,
55+
bool KillSrc, bool RenamableDest = false,
56+
bool RenamableSrc = false) const override;
5757
bool expandPostRAPseudo(MachineInstr &MI) const override;
5858
};
5959

‎llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -54,17 +54,17 @@ bool WebAssemblyInstrInfo::isReallyTriviallyReMaterializable(
5454
}
5555
}
5656

57-
void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
58-
MachineBasicBlock::iterator I,
59-
const DebugLoc &DL, MCRegister DestReg,
60-
MCRegister SrcReg, bool KillSrc,
61-
bool RenamableDest,
62-
bool RenamableSrc) const {
57+
void WebAssemblyInstrInfo::copyReg(MachineBasicBlock &MBB,
58+
MachineBasicBlock::iterator I,
59+
const DebugLoc &DL, Register DestReg,
60+
Register SrcReg, bool KillSrc,
61+
bool RenamableDest,
62+
bool RenamableSrc) const {
6363
// This method is called by post-RA expansion, which expects only pregs to
6464
// exist. However we need to handle both here.
6565
auto &MRI = MBB.getParent()->getRegInfo();
6666
const TargetRegisterClass *RC =
67-
Register::isVirtualRegister(DestReg)
67+
DestReg.isVirtual()
6868
? MRI.getRegClass(DestReg)
6969
: MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg);
7070

‎llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -39,10 +39,10 @@ class WebAssemblyInstrInfo final : public WebAssemblyGenInstrInfo {
3939

4040
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
4141

42-
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
43-
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
44-
bool KillSrc, bool RenamableDest = false,
45-
bool RenamableSrc = false) const override;
42+
void copyReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
43+
const DebugLoc &DL, Register DestReg, Register SrcReg,
44+
bool KillSrc, bool RenamableDest = false,
45+
bool RenamableSrc = false) const override;
4646
MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
4747
unsigned OpIdx1,
4848
unsigned OpIdx2) const override;

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