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llvm/utils/gn/secondary/llvm
include/llvm/TargetParser Expand file tree Collapse file tree 2 files changed +9
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lines changed Original file line number Diff line number Diff line change @@ -14,6 +14,13 @@ tablegen("AArch64TargetParserDef") {
1414 tblgen_target = " //llvm/utils/TableGen:llvm-min-tblgen"
1515}
1616
17+ tablegen (" PPCGenTargetFeatures" ) {
18+ visibility = [ " :gen" ]
19+ args = [ " -gen-target-features" ]
20+ td_file = " //llvm/lib/Target/PowerPC/PPC.td"
21+ tblgen_target = " //llvm/utils/TableGen:llvm-min-tblgen"
22+ }
23+
1724tablegen (" RISCVTargetParserDef" ) {
1825 visibility = [ " :gen" ]
1926 args = [ " -gen-riscv-target-def" ]
@@ -25,6 +32,7 @@ group("gen") {
2532 deps = [
2633 " :AArch64TargetParserDef" ,
2734 " :ARMTargetParserDef" ,
35+ " :PPCGenTargetFeatures" ,
2836 " :RISCVTargetParserDef" ,
2937 ]
3038}
Original file line number Diff line number Diff line change @@ -12,6 +12,7 @@ source_set("Basic") {
1212 " RISCVTargetDefEmitter.cpp" ,
1313 " SDNodeProperties.cpp" ,
1414 " TableGen.cpp" ,
15+ " TargetFeaturesEmitter.cpp" ,
1516 " VTEmitter.cpp" ,
1617 ]
1718}
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