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fixup! [mlir][vector] Tighten the semantics of vector.{load|store}
Address comments from Ben
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2 files changed

+1
-5
lines changed

2 files changed

+1
-5
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mlir/test/Integration/Dialect/Vector/CPU/ArmSME/transpose.mlir

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,10 +14,9 @@ func.func @entry() {
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// Calculate the size of a 32-bit tile, e.g. ZA{n}.s.
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%svl_s = arm_sme.streaming_vl <word>
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%za_s_size = arith.muli %svl_s, %svl_s : index
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// Allocate memory.
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%mem1 = memref.alloca(%za_s_size, %svl_s) : memref<?x?xi32>
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%mem1 = memref.alloca(%svl_s, %svl_s) : memref<?x?xi32>
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// Fill each "row" of "mem1" with row number.
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//

mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-load-store.mlir

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,6 @@ func.func @za0_d_f64() -> i32 {
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// 2.1, 2.1, 2.1, 2.1
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// 3.1, 3.1, 3.1, 3.1
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//
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%tilesize = arith.muli %svl_d, %svl_d : index
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%mem1 = memref.alloca(%svl_d, %svl_d) : memref<?x?xf64>
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%init_0 = arith.constant 0.1 : f64
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scf.for %i = %c0 to %svl_d step %c1_index iter_args(%val = %init_0) -> (f64) {
@@ -171,9 +170,7 @@ func.func @load_store_two_za_s_tiles() -> i32 {
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%svl_s = arm_sme.streaming_vl <word>
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// Allocate memory for two 32-bit element tiles.
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%size_of_tile = arith.muli %svl_s, %svl_s : index
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%svl_s_x_2 = arith.muli %svl_s, %c2_index : index
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%size_of_two_tiles = arith.muli %size_of_tile, %c2_index : index
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%mem1 = memref.alloca(%svl_s_x_2, %svl_s) : memref<?x?xi32>
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// Fill memory that tile 1 will be loaded from with '1' and '2' for tile 2.

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