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[RISCV] Add coverage for missed scalarization of gather/scatter base pointers
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‎llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll‎

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@@ -2373,3 +2373,170 @@ define <vscale x 1 x i8> @mgather_baseidx_zext_nxv1i1_nxv1i8(ptr %base, <vscale
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%v = call <vscale x 1 x i8> @llvm.masked.gather.nxv1i8.nxv1p0(<vscale x 1 x ptr> %ptrs, i32 1, <vscale x 1 x i1> %m, <vscale x 1 x i8> %passthru)
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ret <vscale x 1 x i8> %v
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}
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define <4 x i32> @scalar_prefix(ptr %base, i32 signext %index, <4 x i32> %vecidx) {
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; RV32-LABEL: scalar_prefix:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; RV32-NEXT: vmv.v.x v9, a1
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; RV32-NEXT: vsll.vi v9, v9, 10
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; RV32-NEXT: vadd.vx v9, v9, a0
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; RV32-NEXT: vsll.vi v8, v8, 2
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; RV32-NEXT: vadd.vv v8, v9, v8
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; RV32-NEXT: vluxei32.v v8, (zero), v8
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; RV32-NEXT: ret
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;
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; RV64-LABEL: scalar_prefix:
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; RV64: # %bb.0:
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; RV64-NEXT: li a2, 1024
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; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV64-NEXT: vmv.v.x v10, a0
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; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; RV64-NEXT: vmv.v.x v9, a2
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; RV64-NEXT: vwmaccsu.vx v10, a1, v9
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; RV64-NEXT: li a0, 4
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; RV64-NEXT: vwmaccus.vx v10, a0, v8
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; RV64-NEXT: vluxei64.v v8, (zero), v10
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; RV64-NEXT: ret
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%gep = getelementptr [256 x i32], ptr %base, i32 %index, <4 x i32> %vecidx
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%res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %gep, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
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ret <4 x i32> %res
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}
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define <4 x i32> @scalar_prefix_with_splat(ptr %base, i32 %index, <4 x i32> %vecidx) {
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; RV32-LABEL: scalar_prefix_with_splat:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; RV32-NEXT: vmv.v.x v9, a1
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; RV32-NEXT: vsll.vi v9, v9, 10
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; RV32-NEXT: vadd.vx v9, v9, a0
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; RV32-NEXT: vsll.vi v8, v8, 2
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; RV32-NEXT: vadd.vv v8, v9, v8
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; RV32-NEXT: vluxei32.v v8, (zero), v8
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; RV32-NEXT: ret
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;
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; RV64-LABEL: scalar_prefix_with_splat:
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; RV64: # %bb.0:
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; RV64-NEXT: li a2, 1024
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; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV64-NEXT: vmv.v.x v10, a0
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; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; RV64-NEXT: vmv.v.x v9, a2
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; RV64-NEXT: vwmaccsu.vx v10, a1, v9
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; RV64-NEXT: li a0, 4
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; RV64-NEXT: vwmaccus.vx v10, a0, v8
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; RV64-NEXT: vluxei64.v v8, (zero), v10
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; RV64-NEXT: ret
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%broadcast.splatinsert = insertelement <4 x i32> poison, i32 %index, i32 0
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%broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
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%gep = getelementptr [256 x i32], ptr %base, <4 x i32> %broadcast.splat, <4 x i32> %vecidx
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%res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %gep, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
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ret <4 x i32> %res
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}
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define <4 x i32> @scalar_prefix_with_constant_splat(ptr %base, <4 x i32> %vecidx) {
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; RV32-LABEL: scalar_prefix_with_constant_splat:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a1, 5
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; RV32-NEXT: add a0, a0, a1
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; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; RV32-NEXT: vsll.vi v8, v8, 2
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; RV32-NEXT: vluxei32.v v8, (a0), v8
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; RV32-NEXT: ret
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;
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; RV64-LABEL: scalar_prefix_with_constant_splat:
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; RV64: # %bb.0:
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; RV64-NEXT: li a1, 4
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; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; RV64-NEXT: vwmulsu.vx v10, v8, a1
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; RV64-NEXT: lui a1, 5
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; RV64-NEXT: add a0, a0, a1
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; RV64-NEXT: vluxei64.v v8, (a0), v10
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; RV64-NEXT: ret
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%gep = getelementptr [256 x i32], ptr %base, <4 x i32> splat (i32 20), <4 x i32> %vecidx
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%res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %gep, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
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ret <4 x i32> %res
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}
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define <4 x i32> @reassociate(ptr %base, i32 %index, <4 x i32> %vecidx) {
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; RV32-LABEL: reassociate:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; RV32-NEXT: vsll.vi v8, v8, 10
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; RV32-NEXT: vmv.v.x v9, a1
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; RV32-NEXT: vadd.vx v8, v8, a0
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; RV32-NEXT: vsll.vi v9, v9, 2
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; RV32-NEXT: vadd.vv v8, v8, v9
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; RV32-NEXT: vluxei32.v v8, (zero), v8
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; RV32-NEXT: ret
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;
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; RV64-LABEL: reassociate:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV64-NEXT: vmv.v.x v10, a0
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; RV64-NEXT: li a0, 1024
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; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; RV64-NEXT: vwmaccus.vx v10, a0, v8
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; RV64-NEXT: vmv.v.i v8, 4
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; RV64-NEXT: vwmaccsu.vx v10, a1, v8
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; RV64-NEXT: vluxei64.v v8, (zero), v10
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; RV64-NEXT: ret
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%gep = getelementptr [256 x i32], ptr %base, <4 x i32> %vecidx, i32 %index
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%res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %gep, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
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ret <4 x i32> %res
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}
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define <4 x i32> @reassociate_with_splat(ptr %base, i32 %index, <4 x i32> %vecidx) {
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; RV32-LABEL: reassociate_with_splat:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; RV32-NEXT: vmv.v.x v9, a1
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; RV32-NEXT: vsll.vi v8, v8, 10
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; RV32-NEXT: vadd.vx v8, v8, a0
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; RV32-NEXT: vsll.vi v9, v9, 2
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; RV32-NEXT: vadd.vv v8, v8, v9
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; RV32-NEXT: vluxei32.v v8, (zero), v8
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; RV32-NEXT: ret
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;
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; RV64-LABEL: reassociate_with_splat:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV64-NEXT: vmv.v.x v10, a0
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; RV64-NEXT: li a0, 1024
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; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; RV64-NEXT: vwmaccus.vx v10, a0, v8
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; RV64-NEXT: vmv.v.i v8, 4
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; RV64-NEXT: vwmaccsu.vx v10, a1, v8
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; RV64-NEXT: vluxei64.v v8, (zero), v10
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; RV64-NEXT: ret
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%broadcast.splatinsert = insertelement <4 x i32> poison, i32 %index, i32 0
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%broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> poison, <4 x i32> zeroinitializer
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%gep = getelementptr [256 x i32], ptr %base, <4 x i32> %vecidx, <4 x i32> %broadcast.splat
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%res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %gep, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
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ret <4 x i32> %res
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}
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define <4 x i32> @reassociate_with_constant_splat(ptr %base, i32 %index, <4 x i32> %vecidx) {
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; RV32-LABEL: reassociate_with_constant_splat:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; RV32-NEXT: vsll.vi v8, v8, 10
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; RV32-NEXT: addi a0, a0, 80
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; RV32-NEXT: vluxei32.v v8, (a0), v8
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; RV32-NEXT: ret
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;
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; RV64-LABEL: reassociate_with_constant_splat:
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; RV64: # %bb.0:
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; RV64-NEXT: li a1, 1024
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; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; RV64-NEXT: vwmulsu.vx v10, v8, a1
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; RV64-NEXT: addi a0, a0, 80
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; RV64-NEXT: vluxei64.v v8, (a0), v10
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; RV64-NEXT: ret
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%gep = getelementptr [256 x i32], ptr %base, <4 x i32> %vecidx, <4 x i32> splat (i32 20)
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%res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %gep, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
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ret <4 x i32> %res
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}
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