Skip to content

Commit 19a4135

Browse files
lukel97lukel97
authored
[RISCV][VLOPT] Add support for Single-Width Floating-Point Fused Multiply-Add Instructions (#125652)
These instructions have EEW=SEW for all operands.
1 parent 375df71 commit 19a4135

File tree

3 files changed

+364
-20
lines changed

3 files changed

+364
-20
lines changed

‎llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -451,6 +451,23 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
451451
case RISCV::VFDIV_VF:
452452
case RISCV::VFDIV_VV:
453453
case RISCV::VFRDIV_VF:
454+
// Vector Single-Width Floating-Point Fused Multiply-Add Instructions
455+
case RISCV::VFMACC_VV:
456+
case RISCV::VFMACC_VF:
457+
case RISCV::VFNMACC_VV:
458+
case RISCV::VFNMACC_VF:
459+
case RISCV::VFMSAC_VV:
460+
case RISCV::VFMSAC_VF:
461+
case RISCV::VFNMSAC_VV:
462+
case RISCV::VFNMSAC_VF:
463+
case RISCV::VFMADD_VV:
464+
case RISCV::VFMADD_VF:
465+
case RISCV::VFNMADD_VV:
466+
case RISCV::VFNMADD_VF:
467+
case RISCV::VFMSUB_VV:
468+
case RISCV::VFMSUB_VF:
469+
case RISCV::VFNMSUB_VV:
470+
case RISCV::VFNMSUB_VF:
454471
// Vector Floating-Point Square-Root Instruction
455472
case RISCV::VFSQRT_V:
456473
// Vector Floating-Point Reciprocal Square-Root Estimate Instruction
@@ -1016,6 +1033,23 @@ static bool isSupportedInstr(const MachineInstr &MI) {
10161033
// Vector Widening Floating-Point Multiply
10171034
case RISCV::VFWMUL_VF:
10181035
case RISCV::VFWMUL_VV:
1036+
// Vector Single-Width Floating-Point Fused Multiply-Add Instructions
1037+
case RISCV::VFMACC_VV:
1038+
case RISCV::VFMACC_VF:
1039+
case RISCV::VFNMACC_VV:
1040+
case RISCV::VFNMACC_VF:
1041+
case RISCV::VFMSAC_VV:
1042+
case RISCV::VFMSAC_VF:
1043+
case RISCV::VFNMSAC_VV:
1044+
case RISCV::VFNMSAC_VF:
1045+
case RISCV::VFMADD_VV:
1046+
case RISCV::VFMADD_VF:
1047+
case RISCV::VFNMADD_VV:
1048+
case RISCV::VFNMADD_VF:
1049+
case RISCV::VFMSUB_VV:
1050+
case RISCV::VFMSUB_VF:
1051+
case RISCV::VFNMSUB_VV:
1052+
case RISCV::VFNMSUB_VF:
10191053
// Vector Floating-Point MIN/MAX Instructions
10201054
case RISCV::VFMIN_VF:
10211055
case RISCV::VFMIN_VV:

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll‎

Lines changed: 10 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1444,13 +1444,12 @@ define void @fma_v6bf16(ptr %x, ptr %y, ptr %z) {
14441444
; CHECK-NEXT: vle16.v v8, (a2)
14451445
; CHECK-NEXT: vle16.v v9, (a0)
14461446
; CHECK-NEXT: vle16.v v10, (a1)
1447-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
14481447
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
14491448
; CHECK-NEXT: vfwcvtbf16.f.f.v v14, v9
14501449
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
14511450
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
14521451
; CHECK-NEXT: vfmadd.vv v8, v14, v12
1453-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
1452+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
14541453
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
14551454
; CHECK-NEXT: vse16.v v10, (a0)
14561455
; CHECK-NEXT: ret
@@ -1513,13 +1512,12 @@ define void @fma_v6f16(ptr %x, ptr %y, ptr %z) {
15131512
; ZVFHMIN-NEXT: vle16.v v8, (a2)
15141513
; ZVFHMIN-NEXT: vle16.v v9, (a0)
15151514
; ZVFHMIN-NEXT: vle16.v v10, (a1)
1516-
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
15171515
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
15181516
; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v9
15191517
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
15201518
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
15211519
; ZVFHMIN-NEXT: vfmadd.vv v8, v14, v12
1522-
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
1520+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
15231521
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
15241522
; ZVFHMIN-NEXT: vse16.v v10, (a0)
15251523
; ZVFHMIN-NEXT: ret
@@ -1602,14 +1600,13 @@ define void @fmsub_v6bf16(ptr %x, ptr %y, ptr %z) {
16021600
; CHECK-NEXT: vle16.v v9, (a0)
16031601
; CHECK-NEXT: vle16.v v10, (a1)
16041602
; CHECK-NEXT: lui a1, 8
1605-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
16061603
; CHECK-NEXT: vxor.vx v8, v8, a1
16071604
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
16081605
; CHECK-NEXT: vfwcvtbf16.f.f.v v14, v8
16091606
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
16101607
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
16111608
; CHECK-NEXT: vfmadd.vv v8, v12, v14
1612-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
1609+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
16131610
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
16141611
; CHECK-NEXT: vse16.v v10, (a0)
16151612
; CHECK-NEXT: ret
@@ -1677,14 +1674,13 @@ define void @fmsub_v6f16(ptr %x, ptr %y, ptr %z) {
16771674
; ZVFHMIN-NEXT: vle16.v v9, (a0)
16781675
; ZVFHMIN-NEXT: vle16.v v10, (a1)
16791676
; ZVFHMIN-NEXT: lui a1, 8
1680-
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
16811677
; ZVFHMIN-NEXT: vxor.vx v8, v8, a1
16821678
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
16831679
; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8
16841680
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
16851681
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
16861682
; ZVFHMIN-NEXT: vfmadd.vv v8, v12, v14
1687-
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
1683+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
16881684
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
16891685
; ZVFHMIN-NEXT: vse16.v v10, (a0)
16901686
; ZVFHMIN-NEXT: ret
@@ -3381,14 +3377,13 @@ define void @fma_vf_v6bf16(ptr %x, ptr %y, bfloat %z) {
33813377
; CHECK-NEXT: vle16.v v8, (a1)
33823378
; CHECK-NEXT: vle16.v v9, (a0)
33833379
; CHECK-NEXT: fmv.x.w a1, fa0
3384-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
33853380
; CHECK-NEXT: vmv.v.x v10, a1
33863381
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
33873382
; CHECK-NEXT: vfwcvtbf16.f.f.v v14, v9
33883383
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
33893384
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
33903385
; CHECK-NEXT: vfmadd.vv v8, v14, v12
3391-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
3386+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
33923387
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
33933388
; CHECK-NEXT: vse16.v v10, (a0)
33943389
; CHECK-NEXT: ret
@@ -3452,14 +3447,13 @@ define void @fma_vf_v6f16(ptr %x, ptr %y, half %z) {
34523447
; ZVFHMIN-NEXT: vle16.v v8, (a1)
34533448
; ZVFHMIN-NEXT: vle16.v v9, (a0)
34543449
; ZVFHMIN-NEXT: fmv.x.w a1, fa0
3455-
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
34563450
; ZVFHMIN-NEXT: vmv.v.x v10, a1
34573451
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
34583452
; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v9
34593453
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
34603454
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
34613455
; ZVFHMIN-NEXT: vfmadd.vv v8, v14, v12
3462-
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
3456+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
34633457
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
34643458
; ZVFHMIN-NEXT: vse16.v v10, (a0)
34653459
; ZVFHMIN-NEXT: ret
@@ -3541,14 +3535,13 @@ define void @fma_fv_v6bf16(ptr %x, ptr %y, bfloat %z) {
35413535
; CHECK-NEXT: vle16.v v8, (a1)
35423536
; CHECK-NEXT: vle16.v v9, (a0)
35433537
; CHECK-NEXT: fmv.x.w a1, fa0
3544-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
35453538
; CHECK-NEXT: vmv.v.x v10, a1
35463539
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
35473540
; CHECK-NEXT: vfwcvtbf16.f.f.v v14, v9
35483541
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
35493542
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
35503543
; CHECK-NEXT: vfmadd.vv v8, v14, v12
3551-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
3544+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
35523545
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
35533546
; CHECK-NEXT: vse16.v v10, (a0)
35543547
; CHECK-NEXT: ret
@@ -3612,14 +3605,13 @@ define void @fma_fv_v6f16(ptr %x, ptr %y, half %z) {
36123605
; ZVFHMIN-NEXT: vle16.v v8, (a1)
36133606
; ZVFHMIN-NEXT: vle16.v v9, (a0)
36143607
; ZVFHMIN-NEXT: fmv.x.w a1, fa0
3615-
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
36163608
; ZVFHMIN-NEXT: vmv.v.x v10, a1
36173609
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
36183610
; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v9
36193611
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
36203612
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
36213613
; ZVFHMIN-NEXT: vfmadd.vv v8, v14, v12
3622-
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
3614+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
36233615
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
36243616
; ZVFHMIN-NEXT: vse16.v v10, (a0)
36253617
; ZVFHMIN-NEXT: ret
@@ -3705,15 +3697,14 @@ define void @fmsub_vf_v6bf16(ptr %x, ptr %y, bfloat %z) {
37053697
; CHECK-NEXT: vle16.v v8, (a1)
37063698
; CHECK-NEXT: vle16.v v9, (a0)
37073699
; CHECK-NEXT: lui a1, 8
3708-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
37093700
; CHECK-NEXT: vmv.v.x v10, a2
37103701
; CHECK-NEXT: vxor.vx v8, v8, a1
37113702
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
37123703
; CHECK-NEXT: vfwcvtbf16.f.f.v v14, v8
37133704
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
37143705
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
37153706
; CHECK-NEXT: vfmadd.vv v8, v12, v14
3716-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
3707+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
37173708
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
37183709
; CHECK-NEXT: vse16.v v10, (a0)
37193710
; CHECK-NEXT: ret
@@ -3782,15 +3773,14 @@ define void @fmsub_vf_v6f16(ptr %x, ptr %y, half %z) {
37823773
; ZVFHMIN-NEXT: vle16.v v8, (a1)
37833774
; ZVFHMIN-NEXT: vle16.v v9, (a0)
37843775
; ZVFHMIN-NEXT: lui a1, 8
3785-
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
37863776
; ZVFHMIN-NEXT: vmv.v.x v10, a2
37873777
; ZVFHMIN-NEXT: vxor.vx v8, v8, a1
37883778
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
37893779
; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8
37903780
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
37913781
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
37923782
; ZVFHMIN-NEXT: vfmadd.vv v8, v12, v14
3793-
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
3783+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
37943784
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
37953785
; ZVFHMIN-NEXT: vse16.v v10, (a0)
37963786
; ZVFHMIN-NEXT: ret

0 commit comments

Comments
 (0)