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Copy file name to clipboardExpand all lines: llvm/docs/RISCV/RISCVVectorExtension.rst
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@@ -260,7 +260,7 @@ VMV0 elimination
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Because masked instructions must have the mask register in ``v0``, a specific register class ``vmv0`` is used that contains only one register, ``v0``.
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However register coalescing may end up coleascing copies into ``vmv0``, resulting in instructions with multiple uses of ``vmv0`` that the register allocator can't allocate:
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However register coalescing may end up coalescing copies into ``vmv0``, resulting in instructions with multiple uses of ``vmv0`` that the register allocator can't allocate:
Copy file name to clipboardExpand all lines: llvm/docs/SPIRVUsage.rst
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@@ -188,7 +188,7 @@ list of supported SPIR-V extensions, sorted alphabetically by their extension na
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* - ``SPV_INTEL_variable_length_array``
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- Allows to allocate local arrays whose number of elements is unknown at compile time.
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* - ``SPV_INTEL_joint_matrix``
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- Adds few matrix capabilities on top of SPV_KHR_cooperative_matrix extension, such as matrix prefetch, get element coordinate and checked load/store/construct instructions, tensor float 32 and bfloat type interpretations for multuply-add instruction.
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- Adds few matrix capabilities on top of SPV_KHR_cooperative_matrix extension, such as matrix prefetch, get element coordinate and checked load/store/construct instructions, tensor float 32 and bfloat type interpretations for multiply-add instruction.
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* - ``SPV_KHR_bit_instructions``
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- Enables bit instructions to be used by SPIR-V modules without requiring the Shader capability.
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