Revert "RISCV unwinding enable" (#159790)

DavidSpickett · web-flow · commit 19bc0d6543ae · 2025-09-19T16:19:46.000+01:00
Reverts #158161 Due to reported failures on remote Linux and Swift buildbots.
diff --git a/lldb/include/lldb/Core/Opcode.h b/lldb/include/lldb/Core/Opcode.h
@@ -223,9 +223,7 @@ class Opcode {
   int Dump(Stream *s, uint32_t min_byte_width) const;
 
   const void *GetOpcodeBytes() const {
-    return ((m_type == Opcode::eTypeBytes || m_type == Opcode::eType16_32Tuples)
-                ? m_data.inst.bytes
-                : nullptr);
+    return ((m_type == Opcode::eTypeBytes) ? m_data.inst.bytes : nullptr);
   }
 
   uint32_t GetByteSize() const {
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -33,10 +33,6 @@ LLDB_PLUGIN_DEFINE_ADV(EmulateInstructionRISCV, InstructionRISCV)
 
 namespace lldb_private {
 
-// RISC-V General Purpose Register numbers
-static constexpr uint32_t RISCV_GPR_SP = 2; // x2 is the stack pointer
-static constexpr uint32_t RISCV_GPR_FP = 8; // x8 is the frame pointer
-
 /// Returns all values wrapped in Optional, or std::nullopt if any of the values
 /// is std::nullopt.
 template <typename... Ts>
@@ -112,16 +108,6 @@ static uint32_t FPREncodingToLLDB(uint32_t reg_encode) {
   return LLDB_INVALID_REGNUM;
 }
 
-// Helper function to get register info from GPR encoding
-static std::optional<RegisterInfo>
-GPREncodingToRegisterInfo(EmulateInstructionRISCV &emulator,
-                          uint32_t reg_encode) {
-  uint32_t lldb_reg = GPREncodingToLLDB(reg_encode);
-  if (lldb_reg == LLDB_INVALID_REGNUM)
-    return std::nullopt;
-  return emulator.GetRegisterInfo(eRegisterKindLLDB, lldb_reg);
-}
-
 bool Rd::Write(EmulateInstructionRISCV &emulator, uint64_t value) {
   uint32_t lldb_reg = GPREncodingToLLDB(rd);
   EmulateInstruction::Context ctx;
@@ -244,34 +230,10 @@ Load(EmulateInstructionRISCV &emulator, I inst, uint64_t (*extend)(E)) {
   auto addr = LoadStoreAddr(emulator, inst);
   if (!addr)
     return false;
-
-  // Set up context for the load operation, similar to ARM64.
-  EmulateInstructionRISCV::Context context;
-
-  // Get register info for base register
-  std::optional<RegisterInfo> reg_info_rs1 =
-      GPREncodingToRegisterInfo(emulator, inst.rs1.rs);
-
-  if (!reg_info_rs1)
-    return false;
-
-  // Set context type based on whether this is a stack-based load.
-  if (inst.rs1.rs == RISCV_GPR_SP)
-    context.type = EmulateInstruction::eContextPopRegisterOffStack;
-  else
-    context.type = EmulateInstruction::eContextRegisterLoad;
-
-  // Set the context address information
-  context.SetAddress(*addr);
-
-  // Read from memory with context and write to register.
-  bool success = false;
-  uint64_t value =
-      emulator.ReadMemoryUnsigned(context, *addr, sizeof(T), 0, &success);
-  if (!success)
-    return false;
-
-  return inst.rd.Write(emulator, extend(E(T(value))));
+  return transformOptional(
+             emulator.ReadMem<T>(*addr),
+             [&](T t) { return inst.rd.Write(emulator, extend(E(t))); })
+      .value_or(false);
 }
 
 template <typename I, typename T>
@@ -280,35 +242,9 @@ Store(EmulateInstructionRISCV &emulator, I inst) {
   auto addr = LoadStoreAddr(emulator, inst);
   if (!addr)
     return false;
-
-  // Set up context for the store operation, similar to ARM64.
-  EmulateInstructionRISCV::Context context;
-
-  // Get register info for source and base registers.
-  std::optional<RegisterInfo> reg_info_rs1 =
-      GPREncodingToRegisterInfo(emulator, inst.rs1.rs);
-  std::optional<RegisterInfo> reg_info_rs2 =
-      GPREncodingToRegisterInfo(emulator, inst.rs2.rs);
-
-  if (!reg_info_rs1 || !reg_info_rs2)
-    return false;
-
-  // Set context type based on whether this is a stack-based store.
-  if (inst.rs1.rs == RISCV_GPR_SP)
-    context.type = EmulateInstruction::eContextPushRegisterOnStack;
-  else
-    context.type = EmulateInstruction::eContextRegisterStore;
-
-  // Set the context to show which register is being stored to which base
-  // register + offset.
-  context.SetRegisterToRegisterPlusOffset(*reg_info_rs2, *reg_info_rs1,
-                                          SignExt(inst.imm));
-
-  return transformOptional(inst.rs2.Read(emulator),
-                           [&](uint64_t rs2) {
-                             return emulator.WriteMemoryUnsigned(
-                                 context, *addr, rs2, sizeof(T));
-                           })
+  return transformOptional(
+             inst.rs2.Read(emulator),
+             [&](uint64_t rs2) { return emulator.WriteMem<T>(*addr, rs2); })
       .value_or(false);
 }
 
@@ -801,44 +737,11 @@ class Executor {
   bool operator()(SH inst) { return Store<SH, uint16_t>(m_emu, inst); }
   bool operator()(SW inst) { return Store<SW, uint32_t>(m_emu, inst); }
   bool operator()(ADDI inst) {
-    return transformOptional(
-               inst.rs1.ReadI64(m_emu),
-               [&](int64_t rs1) {
-                 int64_t result = rs1 + int64_t(SignExt(inst.imm));
-                 // Check if this is a stack pointer adjustment.
-                 if (inst.rd.rd == RISCV_GPR_SP &&
-                     inst.rs1.rs == RISCV_GPR_SP) {
-                   EmulateInstruction::Context context;
-                   context.type =
-                       EmulateInstruction::eContextAdjustStackPointer;
-                   context.SetImmediateSigned(SignExt(inst.imm));
-                   uint32_t sp_lldb_reg = GPREncodingToLLDB(RISCV_GPR_SP);
-                   RegisterValue registerValue;
-                   registerValue.SetUInt64(result);
-                   return m_emu.WriteRegister(context, eRegisterKindLLDB,
-                                              sp_lldb_reg, registerValue);
-                 }
-                 // Check if this is setting up the frame pointer.
-                 // addi fp, sp, imm -> fp = sp + imm (frame pointer setup).
-                 if (inst.rd.rd == RISCV_GPR_FP &&
-                     inst.rs1.rs == RISCV_GPR_SP) {
-                   EmulateInstruction::Context context;
-                   context.type = EmulateInstruction::eContextSetFramePointer;
-                   auto sp_reg_info = m_emu.GetRegisterInfo(
-                       eRegisterKindLLDB, GPREncodingToLLDB(RISCV_GPR_SP));
-                   if (sp_reg_info) {
-                     context.SetRegisterPlusOffset(*sp_reg_info,
-                                                   SignExt(inst.imm));
-                   }
-                   uint32_t fp_lldb_reg = GPREncodingToLLDB(RISCV_GPR_FP);
-                   RegisterValue registerValue;
-                   registerValue.SetUInt64(result);
-                   return m_emu.WriteRegister(context, eRegisterKindLLDB,
-                                              fp_lldb_reg, registerValue);
-                 }
-                 // Regular ADDI instruction.
-                 return inst.rd.Write(m_emu, result);
-               })
+    return transformOptional(inst.rs1.ReadI64(m_emu),
+                             [&](int64_t rs1) {
+                               return inst.rd.Write(
+                                   m_emu, rs1 + int64_t(SignExt(inst.imm)));
+                             })
         .value_or(false);
   }
   bool operator()(SLTI inst) {
@@ -1842,61 +1745,6 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind reg_kind,
   return array[reg_index];
 }
 
-bool EmulateInstructionRISCV::SetInstruction(const Opcode &opcode,
-                                             const Address &inst_addr,
-                                             Target *target) {
-  // Call the base class implementation.
-  if (!EmulateInstruction::SetInstruction(opcode, inst_addr, target))
-    return false;
-
-  // Extract instruction data from the opcode.
-  uint32_t inst_data = 0;
-  const void *opcode_data = m_opcode.GetOpcodeBytes();
-  if (!opcode_data)
-    return false;
-
-  if (m_opcode.GetByteSize() == 2) {
-    // 16-bit compressed instruction.
-    const uint16_t *data = static_cast<const uint16_t *>(opcode_data);
-    inst_data = *data;
-  } else if (m_opcode.GetByteSize() == 4) {
-    // 32-bit instruction.
-    const uint32_t *data = static_cast<const uint32_t *>(opcode_data);
-    inst_data = *data;
-  } else {
-    return false;
-  }
-
-  // Decode the instruction.
-  auto decoded_inst = Decode(inst_data);
-  if (!decoded_inst)
-    return false;
-
-  // Store the decoded result.
-  m_decoded = *decoded_inst;
-  return true;
-}
-
-bool EmulateInstructionRISCV::CreateFunctionEntryUnwind(
-    UnwindPlan &unwind_plan) {
-  unwind_plan.Clear();
-  unwind_plan.SetRegisterKind(eRegisterKindLLDB);
-
-  UnwindPlan::Row row;
-
-  row.GetCFAValue().SetIsRegisterPlusOffset(gpr_sp_riscv, 0);
-  row.SetRegisterLocationToSame(gpr_ra_riscv, /*must_replace=*/false);
-  row.SetRegisterLocationToSame(gpr_fp_riscv, /*must_replace=*/false);
-
-  unwind_plan.AppendRow(std::move(row));
-  unwind_plan.SetSourceName("EmulateInstructionRISCV");
-  unwind_plan.SetSourcedFromCompiler(eLazyBoolNo);
-  unwind_plan.SetUnwindPlanValidAtAllInstructions(eLazyBoolYes);
-  unwind_plan.SetUnwindPlanForSignalTrap(eLazyBoolNo);
-  unwind_plan.SetReturnAddressRegister(gpr_ra_riscv);
-  return true;
-}
-
 bool EmulateInstructionRISCV::SetTargetTriple(const ArchSpec &arch) {
   return SupportsThisArch(arch);
 }
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.h b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.h
@@ -61,7 +61,6 @@ class EmulateInstructionRISCV : public EmulateInstruction {
     case eInstructionTypePCModifying:
       return true;
     case eInstructionTypePrologueEpilogue:
-      return true;
     case eInstructionTypeAll:
       return false;
     }
@@ -86,7 +85,6 @@ class EmulateInstructionRISCV : public EmulateInstruction {
     return SupportsThisInstructionType(inst_type);
   }
 
-  bool CreateFunctionEntryUnwind(UnwindPlan &unwind_plan) override;
   bool SetTargetTriple(const ArchSpec &arch) override;
   bool ReadInstruction() override;
   std::optional<uint32_t> GetLastInstrSize() override { return m_last_size; }
@@ -96,8 +94,6 @@ class EmulateInstructionRISCV : public EmulateInstruction {
   std::optional<RegisterInfo> GetRegisterInfo(lldb::RegisterKind reg_kind,
                                               uint32_t reg_num) override;
 
-  bool SetInstruction(const Opcode &opcode, const Address &inst_addr,
-                      Target *target) override;
   std::optional<DecodeResult> ReadInstructionAt(lldb::addr_t addr);
   std::optional<DecodeResult> Decode(uint32_t inst);
   bool Execute(DecodeResult inst, bool ignore_cond);
diff --git a/lldb/unittests/Instruction/CMakeLists.txt b/lldb/unittests/Instruction/CMakeLists.txt
@@ -2,19 +2,14 @@ add_lldb_unittest(EmulatorTests
   ARM64/TestAArch64Emulator.cpp
   LoongArch/TestLoongArchEmulator.cpp
   RISCV/TestRISCVEmulator.cpp
-  RISCV/TestRiscvInstEmulation.cpp
 
   LINK_COMPONENTS
     Support
-    ${LLVM_TARGETS_TO_BUILD}
   LINK_LIBS
     lldbCore
     lldbSymbol
     lldbTarget
     lldbPluginInstructionARM64
     lldbPluginInstructionLoongArch
     lldbPluginInstructionRISCV
-    lldbPluginDisassemblerLLVMC
-    lldbPluginUnwindAssemblyInstEmulation
-    lldbPluginProcessUtility
   )
diff --git a/lldb/unittests/Instruction/RISCV/TestRiscvInstEmulation.cpp b/lldb/unittests/Instruction/RISCV/TestRiscvInstEmulation.cpp

Original file line number	Diff line number	Diff line change
`@@ -223,9 +223,7 @@ class Opcode {`
`223`	`223`	`int Dump(Stream *s, uint32_t min_byte_width) const;`
`224`	`224`
`225`	`225`	`const void *GetOpcodeBytes() const {`
`226`		`- return ((m_type == Opcode::eTypeBytes \|\| m_type == Opcode::eType16_32Tuples)`
`227`		`- ? m_data.inst.bytes`
`228`		`- : nullptr);`
	`226`	`+ return ((m_type == Opcode::eTypeBytes) ? m_data.inst.bytes : nullptr);`
`229`	`227`	`}`
`230`	`228`
`231`	`229`	`uint32_t GetByteSize() const {`