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[AArch64] Use MCRegister in more places. NFC
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4 files changed

+80
-83
lines changed

4 files changed

+80
-83
lines changed

‎llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp‎

Lines changed: 45 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -136,8 +136,8 @@ class AArch64AsmParser : public MCTargetAsmParser {
136136
assert(Predicated);
137137
return ElementSize;
138138
}
139-
unsigned getDstReg() const { return Dst; }
140-
unsigned getPgReg() const {
139+
MCRegister getDstReg() const { return Dst; }
140+
MCRegister getPgReg() const {
141141
assert(Predicated);
142142
return Pg;
143143
}
@@ -146,8 +146,8 @@ class AArch64AsmParser : public MCTargetAsmParser {
146146
bool Active = false;
147147
bool Predicated = false;
148148
unsigned ElementSize;
149-
unsigned Dst;
150-
unsigned Pg;
149+
MCRegister Dst;
150+
MCRegister Pg;
151151
} NextPrefix;
152152

153153
AArch64TargetStreamer &getTargetStreamer() {
@@ -5234,7 +5234,7 @@ bool AArch64AsmParser::parseInstruction(ParseInstructionInfo &Info,
52345234
return false;
52355235
}
52365236

5237-
static inline bool isMatchingOrAlias(unsigned ZReg, unsigned Reg) {
5237+
static inline bool isMatchingOrAlias(MCRegister ZReg, MCRegister Reg) {
52385238
assert((ZReg >= AArch64::Z0) && (ZReg <= AArch64::Z31));
52395239
return (ZReg == ((Reg - AArch64::B0) + AArch64::Z0)) ||
52405240
(ZReg == ((Reg - AArch64::H0) + AArch64::Z0)) ||
@@ -5322,7 +5322,7 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
53225322
if (IsWindowsArm64EC) {
53235323
for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
53245324
if (Inst.getOperand(i).isReg()) {
5325-
unsigned Reg = Inst.getOperand(i).getReg();
5325+
MCRegister Reg = Inst.getOperand(i).getReg();
53265326
// At this point, vector registers are matched to their
53275327
// appropriately sized alias.
53285328
if ((Reg == AArch64::W13 || Reg == AArch64::X13) ||
@@ -5351,9 +5351,9 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
53515351
case AArch64::LDPWpre:
53525352
case AArch64::LDPXpost:
53535353
case AArch64::LDPXpre: {
5354-
unsigned Rt = Inst.getOperand(1).getReg();
5355-
unsigned Rt2 = Inst.getOperand(2).getReg();
5356-
unsigned Rn = Inst.getOperand(3).getReg();
5354+
MCRegister Rt = Inst.getOperand(1).getReg();
5355+
MCRegister Rt2 = Inst.getOperand(2).getReg();
5356+
MCRegister Rn = Inst.getOperand(3).getReg();
53575357
if (RI->isSubRegisterEq(Rn, Rt))
53585358
return Error(Loc[0], "unpredictable LDP instruction, writeback base "
53595359
"is also a destination");
@@ -5376,8 +5376,8 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
53765376
case AArch64::LDPSWi:
53775377
case AArch64::LDPWi:
53785378
case AArch64::LDPXi: {
5379-
unsigned Rt = Inst.getOperand(0).getReg();
5380-
unsigned Rt2 = Inst.getOperand(1).getReg();
5379+
MCRegister Rt = Inst.getOperand(0).getReg();
5380+
MCRegister Rt2 = Inst.getOperand(1).getReg();
53815381
if (Rt == Rt2)
53825382
return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt");
53835383
break;
@@ -5389,8 +5389,8 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
53895389
case AArch64::LDPSpost:
53905390
case AArch64::LDPSpre:
53915391
case AArch64::LDPSWpost: {
5392-
unsigned Rt = Inst.getOperand(1).getReg();
5393-
unsigned Rt2 = Inst.getOperand(2).getReg();
5392+
MCRegister Rt = Inst.getOperand(1).getReg();
5393+
MCRegister Rt2 = Inst.getOperand(2).getReg();
53945394
if (Rt == Rt2)
53955395
return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt");
53965396
break;
@@ -5405,9 +5405,9 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
54055405
case AArch64::STPWpre:
54065406
case AArch64::STPXpost:
54075407
case AArch64::STPXpre: {
5408-
unsigned Rt = Inst.getOperand(1).getReg();
5409-
unsigned Rt2 = Inst.getOperand(2).getReg();
5410-
unsigned Rn = Inst.getOperand(3).getReg();
5408+
MCRegister Rt = Inst.getOperand(1).getReg();
5409+
MCRegister Rt2 = Inst.getOperand(2).getReg();
5410+
MCRegister Rn = Inst.getOperand(3).getReg();
54115411
if (RI->isSubRegisterEq(Rn, Rt))
54125412
return Error(Loc[0], "unpredictable STP instruction, writeback base "
54135413
"is also a source");
@@ -5438,8 +5438,8 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
54385438
case AArch64::LDRSWpost:
54395439
case AArch64::LDRWpost:
54405440
case AArch64::LDRXpost: {
5441-
unsigned Rt = Inst.getOperand(1).getReg();
5442-
unsigned Rn = Inst.getOperand(2).getReg();
5441+
MCRegister Rt = Inst.getOperand(1).getReg();
5442+
MCRegister Rn = Inst.getOperand(2).getReg();
54435443
if (RI->isSubRegisterEq(Rn, Rt))
54445444
return Error(Loc[0], "unpredictable LDR instruction, writeback base "
54455445
"is also a source");
@@ -5457,8 +5457,8 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
54575457
case AArch64::STRHpre:
54585458
case AArch64::STRWpre:
54595459
case AArch64::STRXpre: {
5460-
unsigned Rt = Inst.getOperand(1).getReg();
5461-
unsigned Rn = Inst.getOperand(2).getReg();
5460+
MCRegister Rt = Inst.getOperand(1).getReg();
5461+
MCRegister Rn = Inst.getOperand(2).getReg();
54625462
if (RI->isSubRegisterEq(Rn, Rt))
54635463
return Error(Loc[0], "unpredictable STR instruction, writeback base "
54645464
"is also a source");
@@ -5472,9 +5472,9 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
54725472
case AArch64::STLXRH:
54735473
case AArch64::STLXRW:
54745474
case AArch64::STLXRX: {
5475-
unsigned Rs = Inst.getOperand(0).getReg();
5476-
unsigned Rt = Inst.getOperand(1).getReg();
5477-
unsigned Rn = Inst.getOperand(2).getReg();
5475+
MCRegister Rs = Inst.getOperand(0).getReg();
5476+
MCRegister Rt = Inst.getOperand(1).getReg();
5477+
MCRegister Rn = Inst.getOperand(2).getReg();
54785478
if (RI->isSubRegisterEq(Rt, Rs) ||
54795479
(RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP))
54805480
return Error(Loc[0],
@@ -5485,10 +5485,10 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
54855485
case AArch64::STXPX:
54865486
case AArch64::STLXPW:
54875487
case AArch64::STLXPX: {
5488-
unsigned Rs = Inst.getOperand(0).getReg();
5489-
unsigned Rt1 = Inst.getOperand(1).getReg();
5490-
unsigned Rt2 = Inst.getOperand(2).getReg();
5491-
unsigned Rn = Inst.getOperand(3).getReg();
5488+
MCRegister Rs = Inst.getOperand(0).getReg();
5489+
MCRegister Rt1 = Inst.getOperand(1).getReg();
5490+
MCRegister Rt2 = Inst.getOperand(2).getReg();
5491+
MCRegister Rn = Inst.getOperand(3).getReg();
54925492
if (RI->isSubRegisterEq(Rt1, Rs) || RI->isSubRegisterEq(Rt2, Rs) ||
54935493
(RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP))
54945494
return Error(Loc[0],
@@ -5497,8 +5497,8 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
54975497
}
54985498
case AArch64::LDRABwriteback:
54995499
case AArch64::LDRAAwriteback: {
5500-
unsigned Xt = Inst.getOperand(0).getReg();
5501-
unsigned Xn = Inst.getOperand(1).getReg();
5500+
MCRegister Xt = Inst.getOperand(0).getReg();
5501+
MCRegister Xn = Inst.getOperand(1).getReg();
55025502
if (Xt == Xn)
55035503
return Error(Loc[0],
55045504
"unpredictable LDRA instruction, writeback base"
@@ -5605,12 +5605,12 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
56055605
case AArch64::CPYETWN:
56065606
case AArch64::CPYETRN:
56075607
case AArch64::CPYETN: {
5608-
unsigned Xd_wb = Inst.getOperand(0).getReg();
5609-
unsigned Xs_wb = Inst.getOperand(1).getReg();
5610-
unsigned Xn_wb = Inst.getOperand(2).getReg();
5611-
unsigned Xd = Inst.getOperand(3).getReg();
5612-
unsigned Xs = Inst.getOperand(4).getReg();
5613-
unsigned Xn = Inst.getOperand(5).getReg();
5608+
MCRegister Xd_wb = Inst.getOperand(0).getReg();
5609+
MCRegister Xs_wb = Inst.getOperand(1).getReg();
5610+
MCRegister Xn_wb = Inst.getOperand(2).getReg();
5611+
MCRegister Xd = Inst.getOperand(3).getReg();
5612+
MCRegister Xs = Inst.getOperand(4).getReg();
5613+
MCRegister Xn = Inst.getOperand(5).getReg();
56145614
if (Xd_wb != Xd)
56155615
return Error(Loc[0],
56165616
"invalid CPY instruction, Xd_wb and Xd do not match");
@@ -5655,11 +5655,11 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
56555655
case AArch64::MOPSSETGET:
56565656
case AArch64::MOPSSETGEN:
56575657
case AArch64::MOPSSETGETN: {
5658-
unsigned Xd_wb = Inst.getOperand(0).getReg();
5659-
unsigned Xn_wb = Inst.getOperand(1).getReg();
5660-
unsigned Xd = Inst.getOperand(2).getReg();
5661-
unsigned Xn = Inst.getOperand(3).getReg();
5662-
unsigned Xm = Inst.getOperand(4).getReg();
5658+
MCRegister Xd_wb = Inst.getOperand(0).getReg();
5659+
MCRegister Xn_wb = Inst.getOperand(1).getReg();
5660+
MCRegister Xd = Inst.getOperand(2).getReg();
5661+
MCRegister Xn = Inst.getOperand(3).getReg();
5662+
MCRegister Xm = Inst.getOperand(4).getReg();
56635663
if (Xd_wb != Xd)
56645664
return Error(Loc[0],
56655665
"invalid SET instruction, Xd_wb and Xd do not match");
@@ -6451,7 +6451,7 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
64516451
// GPR64. Twiddle it here if necessary.
64526452
AArch64Operand &Op = static_cast<AArch64Operand &>(*Operands[2]);
64536453
if (Op.isScalarReg()) {
6454-
unsigned Reg = getXRegFromWReg(Op.getReg());
6454+
MCRegister Reg = getXRegFromWReg(Op.getReg());
64556455
Operands[2] = AArch64Operand::CreateReg(Reg, RegKind::Scalar,
64566456
Op.getStartLoc(), Op.getEndLoc(),
64576457
getContext());
@@ -6467,7 +6467,7 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
64676467
// GPR64. Twiddle it here if necessary.
64686468
AArch64Operand &Op = static_cast<AArch64Operand &>(*Operands[2]);
64696469
if (Op.isScalarReg()) {
6470-
unsigned Reg = getXRegFromWReg(Op.getReg());
6470+
MCRegister Reg = getXRegFromWReg(Op.getReg());
64716471
Operands[2] = AArch64Operand::CreateReg(Reg, RegKind::Scalar,
64726472
Op.getStartLoc(),
64736473
Op.getEndLoc(), getContext());
@@ -6484,7 +6484,7 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
64846484
// GPR32. Twiddle it here if necessary.
64856485
AArch64Operand &Op = static_cast<AArch64Operand &>(*Operands[1]);
64866486
if (Op.isScalarReg()) {
6487-
unsigned Reg = getWRegFromXReg(Op.getReg());
6487+
MCRegister Reg = getWRegFromXReg(Op.getReg());
64886488
Operands[1] = AArch64Operand::CreateReg(Reg, RegKind::Scalar,
64896489
Op.getStartLoc(),
64906490
Op.getEndLoc(), getContext());
@@ -7907,7 +7907,7 @@ ParseStatus AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) {
79077907
return Error(E, "expected second odd register of a consecutive same-size "
79087908
"even/odd register pair");
79097909

7910-
unsigned Pair = 0;
7910+
MCRegister Pair;
79117911
if (isXReg) {
79127912
Pair = RI->getMatchingSuperReg(FirstReg, AArch64::sube64,
79137913
&AArch64MCRegisterClasses[AArch64::XSeqPairsClassRegClassID]);
@@ -8047,7 +8047,7 @@ ParseStatus AArch64AsmParser::tryParseGPR64x8(OperandVector &Operands) {
80478047

80488048
MCContext &ctx = getContext();
80498049
const MCRegisterInfo *RI = ctx.getRegisterInfo();
8050-
int X8Reg = RI->getMatchingSuperReg(
8050+
MCRegister X8Reg = RI->getMatchingSuperReg(
80518051
XReg, AArch64::x8sub_0,
80528052
&AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID]);
80538053
if (!X8Reg)

‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -622,7 +622,7 @@ class DarwinAArch64AsmBackend : public AArch64AsmBackend {
622622
return CU::UNWIND_ARM64_MODE_DWARF;
623623
case MCCFIInstruction::OpDefCfa: {
624624
// Defines a frame pointer.
625-
unsigned XReg =
625+
MCRegister XReg =
626626
getXRegFromWReg(*MRI.getLLVMRegNum(Inst.getRegister(), true));
627627

628628
// Other CFA registers than FP are not supported by compact unwind.

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