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davemgreendavemgreen
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[GlobalISel] Allow more illegal vector types in params/returns. (#95514)
This helps some of the testing of illegal types, allowing us to pass them into and out of functions. The AMD tests no longer fail, but I am unsure whether they are correct. They fail later on in the pipeline for GISel, and during lowering ret for SDAG.
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10 files changed

+855
-20
lines changed

10 files changed

+855
-20
lines changed

‎llvm/lib/CodeGen/GlobalISel/CallLowering.cpp‎

Lines changed: 17 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -471,13 +471,15 @@ static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef<Register> OrigRegs,
471471
// Deal with vector with 64-bit elements decomposed to 32-bit
472472
// registers. Need to create intermediate 64-bit elements.
473473
SmallVector<Register, 8> EltMerges;
474-
int PartsPerElt = DstEltTy.getSizeInBits() / PartLLT.getSizeInBits();
475-
476-
assert(DstEltTy.getSizeInBits() % PartLLT.getSizeInBits() == 0);
474+
int PartsPerElt =
475+
divideCeil(DstEltTy.getSizeInBits(), PartLLT.getSizeInBits());
476+
LLT ExtendedPartTy = LLT::scalar(PartLLT.getSizeInBits() * PartsPerElt);
477477

478478
for (int I = 0, NumElts = LLTy.getNumElements(); I != NumElts; ++I) {
479479
auto Merge =
480-
B.buildMergeLikeInstr(RealDstEltTy, Regs.take_front(PartsPerElt));
480+
B.buildMergeLikeInstr(ExtendedPartTy, Regs.take_front(PartsPerElt));
481+
if (ExtendedPartTy.getSizeInBits() > RealDstEltTy.getSizeInBits())
482+
Merge = B.buildTrunc(RealDstEltTy, Merge);
481483
// Fix the type in case this is really a vector of pointers.
482484
MRI.setType(Merge.getReg(0), RealDstEltTy);
483485
EltMerges.push_back(Merge.getReg(0));
@@ -574,6 +576,17 @@ static void buildCopyToRegs(MachineIRBuilder &B, ArrayRef<Register> DstRegs,
574576
return;
575577
}
576578

579+
if (SrcTy.isVector() && !PartTy.isVector() &&
580+
SrcTy.getScalarSizeInBits() > PartTy.getSizeInBits()) {
581+
LLT ExtTy =
582+
LLT::vector(SrcTy.getElementCount(),
583+
LLT::scalar(PartTy.getScalarSizeInBits() * DstRegs.size() /
584+
SrcTy.getNumElements()));
585+
auto Ext = B.buildAnyExt(ExtTy, SrcReg);
586+
B.buildUnmerge(DstRegs, Ext);
587+
return;
588+
}
589+
577590
MachineRegisterInfo &MRI = *B.getMRI();
578591
LLT DstTy = MRI.getType(DstRegs[0]);
579592
LLT LCMTy = getCoverTy(SrcTy, PartTy);

‎llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -406,14 +406,13 @@ bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
406406
ExtendOp = TargetOpcode::G_ZEXT;
407407

408408
LLT NewLLT(NewVT);
409-
LLT OldLLT(MVT::getVT(CurArgInfo.Ty));
409+
LLT OldLLT = getLLTForType(*CurArgInfo.Ty, DL);
410410
CurArgInfo.Ty = EVT(NewVT).getTypeForEVT(Ctx);
411411
// Instead of an extend, we might have a vector type which needs
412412
// padding with more elements, e.g. <2 x half> -> <4 x half>.
413413
if (NewVT.isVector()) {
414414
if (OldLLT.isVector()) {
415415
if (NewLLT.getNumElements() > OldLLT.getNumElements()) {
416-
417416
CurVReg =
418417
MIRBuilder.buildPadVectorWithUndefElements(NewLLT, CurVReg)
419418
.getReg(0);

‎llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll‎

Lines changed: 458 additions & 6 deletions
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‎llvm/test/CodeGen/AArch64/GlobalISel/vec-param.ll‎

Lines changed: 344 additions & 0 deletions
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‎llvm/test/CodeGen/AArch64/sadd_sat_vec.ll‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,6 @@
33
; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
44

55
; CHECK-GI: warning: Instruction selection used fallback path for v2i8
6-
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v12i8
76
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v16i4
87
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v16i1
98
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v2i128

‎llvm/test/CodeGen/AArch64/ssub_sat_vec.ll‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,6 @@
33
; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
44

55
; CHECK-GI: warning: Instruction selection used fallback path for v2i8
6-
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v12i8
76
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v16i4
87
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v16i1
98
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v2i128

‎llvm/test/CodeGen/AArch64/uadd_sat_vec.ll‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,6 @@
33
; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
44

55
; CHECK-GI: warning: Instruction selection used fallback path for v2i8
6-
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v12i8
76
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v16i4
87
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v16i1
98
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v2i128

‎llvm/test/CodeGen/AArch64/usub_sat_vec.ll‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,6 @@
33
; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
44

55
; CHECK-GI: warning: Instruction selection used fallback path for v2i8
6-
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v12i8
76
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v16i4
87
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v16i1
98
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v2i128

‎llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.v2i65.ll‎

Lines changed: 15 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,20 @@
1-
; XFAIL: *
2-
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=irtranslator -verify-machineinstrs -o - %s
1+
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=irtranslator -o - %s | FileCheck %s
33

44
define <2 x i65> @v2i65_func_void() #0 {
5+
; CHECK-LABEL: name: v2i65_func_void
6+
; CHECK: bb.1 (%ir-block.0):
7+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
8+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s65>) = G_LOAD [[DEF]](p1) :: (load (<2 x s65>) from `ptr addrspace(1) undef`, align 32, addrspace 1)
9+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s96>) = G_ANYEXT [[LOAD]](<2 x s65>)
10+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ANYEXT]](<2 x s96>)
11+
; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)
12+
; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)
13+
; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)
14+
; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)
15+
; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32)
16+
; CHECK-NEXT: $vgpr5 = COPY [[UV5]](s32)
17+
; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5
518
%val = load <2 x i65>, ptr addrspace(1) undef
619
ret <2 x i65> %val
720
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.v2i65.ll‎

Lines changed: 20 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,25 @@
1-
; XFAIL: *
2-
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji -stop-after=irtranslator -verify-machineinstrs -o - %s
1+
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji -stop-after=irtranslator -o - %s | FileCheck %s
33

44
define void @void_func_v2i65(<2 x i65> %arg0) #0 {
5+
; CHECK-LABEL: name: void_func_v2i65
6+
; CHECK: bb.1 (%ir-block.0):
7+
; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
8+
; CHECK-NEXT: {{ $}}
9+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
10+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
11+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
12+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
13+
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
14+
; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
15+
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
16+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s65) = G_TRUNC [[MV]](s96)
17+
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32)
18+
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s65) = G_TRUNC [[MV1]](s96)
19+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s65>) = G_BUILD_VECTOR [[TRUNC]](s65), [[TRUNC1]](s65)
20+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
21+
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s65>), [[DEF]](p1) :: (store (<2 x s65>) into `ptr addrspace(1) undef`, align 32, addrspace 1)
22+
; CHECK-NEXT: SI_RETURN
523
store <2 x i65> %arg0, ptr addrspace(1) undef
624
ret void
725
}

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