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2 files changed

+8
-9
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2 files changed

+8
-9
lines changed

llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1155,7 +1155,7 @@ bool NVPTXDAGToDAGISel::tryLoad(SDNode *N) {
11551155
return true;
11561156
}
11571157

1158-
static bool isVectorElementTypeUpsized(EVT EltVT) {
1158+
static bool isSubVectorPackedInI32(EVT EltVT) {
11591159
// Despite vectors like v8i8, v16i8, v8i16 being within the bit-limit for
11601160
// total load/store size, PTX syntax only supports v2/v4. Thus, we can't use
11611161
// vectorized loads/stores with the actual element type for i8/i16 as that
@@ -1213,7 +1213,7 @@ bool NVPTXDAGToDAGISel::tryLoadVector(SDNode *N) {
12131213
return false;
12141214
}
12151215

1216-
if (isVectorElementTypeUpsized(EltVT)) {
1216+
if (isSubVectorPackedInI32(EltVT)) {
12171217
EltVT = MVT::i32;
12181218
FromType = NVPTX::PTXLdStInstCode::Untyped;
12191219
}
@@ -1514,7 +1514,7 @@ bool NVPTXDAGToDAGISel::tryStoreVector(SDNode *N) {
15141514
return false;
15151515
}
15161516

1517-
if (isVectorElementTypeUpsized(EltVT)) {
1517+
if (isSubVectorPackedInI32(EltVT)) {
15181518
EltVT = MVT::i32;
15191519
ToType = NVPTX::PTXLdStInstCode::Untyped;
15201520
}

llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3204,16 +3204,15 @@ NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
32043204
// Combine individual elements into v2[i,f,bf]16/v4i8 subvectors to be
32053205
// stored as b32s
32063206
const unsigned NumEltsPerSubVector = EltVT.getVectorNumElements();
3207-
for (const auto I : llvm::seq(NumElts)) {
3207+
for (const unsigned I : llvm::seq(NumElts)) {
32083208
SmallVector<SDValue, 4> SubVectorElts;
32093209
DAG.ExtractVectorElements(Val, SubVectorElts, I * NumEltsPerSubVector,
32103210
NumEltsPerSubVector);
3211-
SDValue SubVector = DAG.getBuildVector(EltVT, DL, SubVectorElts);
3212-
Ops.push_back(SubVector);
3211+
Ops.push_back(DAG.getBuildVector(EltVT, DL, SubVectorElts));
32133212
}
32143213
} else {
32153214
SDValue V = DAG.getBitcast(MVT::getVectorVT(EltVT, NumElts), Val);
3216-
for (const auto I : llvm::seq(NumElts)) {
3215+
for (const unsigned I : llvm::seq(NumElts)) {
32173216
SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, V,
32183217
DAG.getIntPtrConstant(I, DL));
32193218

@@ -5818,12 +5817,12 @@ static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
58185817
ResVT.getVectorNumElements());
58195818
// Generate EXTRACT_VECTOR_ELTs to split v2[i,f,bf]16/v4i8 subvectors back
58205819
// into individual elements.
5821-
for (const auto I : llvm::seq(NumElts)) {
5820+
for (const unsigned I : llvm::seq(NumElts)) {
58225821
SDValue SubVector = NewLD.getValue(I);
58235822
DAG.ExtractVectorElements(SubVector, ScalarRes);
58245823
}
58255824
} else {
5826-
for (const auto I : llvm::seq(NumElts)) {
5825+
for (const unsigned I : llvm::seq(NumElts)) {
58275826
SDValue Res = NewLD.getValue(I);
58285827
if (LoadEltVT != EltVT)
58295828
Res = DAG.getNode(ISD::TRUNCATE, DL, EltVT, Res);

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