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danilamldanilaml
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[AArch64][InstCombine] Eliminate redundant barrier intrinsics (#112023)
If there are no memory ops on the path from one dmb to another then one barrier can be eliminated.
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‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,10 @@ static cl::opt<unsigned>
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BaseHistCntCost("aarch64-base-histcnt-cost", cl::init(8), cl::Hidden,
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cl::desc("The cost of a histcnt instruction"));
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static cl::opt<unsigned> DMBLookaheadThreshold(
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"dmb-lookahead-threshold", cl::init(10), cl::Hidden,
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cl::desc("The number of instructions to search for a redundant dmb"));
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6973
namespace {
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class TailFoldingOption {
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// These bitfields will only ever be set to something non-zero in operator=,
@@ -2152,13 +2156,40 @@ static std::optional<Instruction *> instCombineSVEInsr(InstCombiner &IC,
21522156
return std::nullopt;
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}
21542158

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static std::optional<Instruction *> instCombineDMB(InstCombiner &IC,
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IntrinsicInst &II) {
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// If this barrier is post-dominated by identical one we can remove it
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auto *NI = II.getNextNonDebugInstruction();
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unsigned LookaheadThreshold = DMBLookaheadThreshold;
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auto CanSkipOver = [](Instruction *I) {
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return !I->mayReadOrWriteMemory() && !I->mayHaveSideEffects();
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};
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while (LookaheadThreshold-- && CanSkipOver(NI)) {
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auto *NIBB = NI->getParent();
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NI = NI->getNextNonDebugInstruction();
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if (!NI) {
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if (auto *SuccBB = NIBB->getUniqueSuccessor())
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NI = SuccBB->getFirstNonPHIOrDbgOrLifetime();
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else
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break;
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}
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}
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auto *NextII = dyn_cast_or_null<IntrinsicInst>(NI);
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if (NextII && II.isIdenticalTo(NextII))
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return IC.eraseInstFromFunction(II);
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return std::nullopt;
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}
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std::optional<Instruction *>
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AArch64TTIImpl::instCombineIntrinsic(InstCombiner &IC,
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IntrinsicInst &II) const {
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Intrinsic::ID IID = II.getIntrinsicID();
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switch (IID) {
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default:
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break;
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case Intrinsic::aarch64_dmb:
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return instCombineDMB(IC, II);
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case Intrinsic::aarch64_sve_fcvt_bf16f32_v2:
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case Intrinsic::aarch64_sve_fcvt_f16f32:
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case Intrinsic::aarch64_sve_fcvt_f16f64:

‎llvm/test/Transforms/InstCombine/AArch64/dmb-intrinsics.ll‎

Lines changed: 220 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,220 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -S -passes=instcombine < %s | FileCheck %s
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; ARM64 dmb intrinsics
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target triple = "aarch64-unknown-linux-gnu"
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declare void @llvm.aarch64.dmb(i32)
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declare void @llvm.aarch64.dsb(i32)
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declare void @clobber()
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declare void @pure() memory(none) willreturn nounwind
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declare i32 @llvm.ctlz.i32(i32, i1)
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define void @simple() #0 {
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; CHECK-LABEL: define void @simple() {
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; CHECK-NEXT: call void @llvm.aarch64.dmb(i32 10)
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; CHECK-NEXT: ret void
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;
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call void @llvm.aarch64.dmb(i32 10)
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call void @llvm.aarch64.dmb(i32 10)
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ret void
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}
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; dmb ish (0xb) is technically stronger than ishst (0xa) but we don't merge for now
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define void @simple_nonmatching() #0 {
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; CHECK-LABEL: define void @simple_nonmatching() {
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; CHECK-NEXT: call void @llvm.aarch64.dmb(i32 10)
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; CHECK-NEXT: call void @llvm.aarch64.dmb(i32 11)
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; CHECK-NEXT: ret void
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;
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call void @llvm.aarch64.dmb(i32 10)
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call void @llvm.aarch64.dmb(i32 11)
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ret void
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}
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define ptr @simple_safe_instruction(ptr %p) #0 {
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; CHECK-LABEL: define ptr @simple_safe_instruction(
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; CHECK-SAME: ptr [[P:%.*]]) {
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; CHECK-NEXT: [[RES:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 8
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; CHECK-NEXT: call void @llvm.aarch64.dmb(i32 10)
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; CHECK-NEXT: ret ptr [[RES]]
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;
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call void @llvm.aarch64.dmb(i32 10)
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%res = getelementptr inbounds i8, ptr %p, i32 8
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call void @llvm.aarch64.dmb(i32 10)
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ret ptr %res
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}
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define i32 @simple_safe_intrinsic(i32 %n) #0 {
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; CHECK-LABEL: define i32 @simple_safe_intrinsic(
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; CHECK-SAME: i32 [[N:%.*]]) {
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; CHECK-NEXT: [[RES:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[N]], i1 false)
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; CHECK-NEXT: call void @llvm.aarch64.dmb(i32 10)
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; CHECK-NEXT: ret i32 [[RES]]
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;
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call void @llvm.aarch64.dmb(i32 10)
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%res = call i32 @llvm.ctlz.i32(i32 %n, i1 false)
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call void @llvm.aarch64.dmb(i32 10)
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ret i32 %res
59+
}
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define void @simple_unsafe_intrinsic() #0 {
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; CHECK-LABEL: define void @simple_unsafe_intrinsic() {
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; CHECK-NEXT: call void @llvm.aarch64.dmb(i32 10)
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; CHECK-NEXT: call void @llvm.aarch64.dsb(i32 10)
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; CHECK-NEXT: call void @llvm.aarch64.dmb(i32 10)
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; CHECK-NEXT: ret void
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;
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call void @llvm.aarch64.dmb(i32 10)
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call void @llvm.aarch64.dsb(i32 10)
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call void @llvm.aarch64.dmb(i32 10)
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ret void
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}
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define void @simple_safe_unsafe_instruction(ptr %p) #0 {
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; CHECK-LABEL: define void @simple_safe_unsafe_instruction(
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; CHECK-SAME: ptr [[P:%.*]]) {
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; CHECK-NEXT: call void @llvm.aarch64.dmb(i32 10)
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; CHECK-NEXT: store i32 42, ptr [[P]], align 4
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; CHECK-NEXT: call void @llvm.aarch64.dmb(i32 10)
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; CHECK-NEXT: ret void
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;
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call void @llvm.aarch64.dmb(i32 10)
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store i32 42, ptr %p
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call void @llvm.aarch64.dmb(i32 10)
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ret void
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}
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define void @simple_safe_unsafe_call(ptr %p) #0 {
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; CHECK-LABEL: define void @simple_safe_unsafe_call(
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; CHECK-SAME: ptr [[P:%.*]]) {
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; CHECK-NEXT: call void @llvm.aarch64.dmb(i32 10)
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; CHECK-NEXT: call void @clobber()
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; CHECK-NEXT: call void @llvm.aarch64.dmb(i32 10)
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; CHECK-NEXT: ret void
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;
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call void @llvm.aarch64.dmb(i32 10)
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call void @clobber()
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call void @llvm.aarch64.dmb(i32 10)
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ret void
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}
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102+
define void @simple_safe_safe_call(ptr %p) #0 {
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; CHECK-LABEL: define void @simple_safe_safe_call(
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; CHECK-SAME: ptr [[P:%.*]]) {
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; CHECK-NEXT: call void @llvm.aarch64.dmb(i32 10)
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; CHECK-NEXT: ret void
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;
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call void @llvm.aarch64.dmb(i32 10)
109+
call void @pure()
110+
call void @llvm.aarch64.dmb(i32 10)
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ret void
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}
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define void @multiple_bbs1(i1 %f) #0 {
115+
; CHECK-LABEL: define void @multiple_bbs1(
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; CHECK-SAME: i1 [[F:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br i1 [[F]], label %[[BB_T:.*]], label %[[BB_F:.*]]
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; CHECK: [[BB_T]]:
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; CHECK-NEXT: br label %[[EXIT:.*]]
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; CHECK: [[BB_F]]:
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; CHECK-NEXT: br label %[[EXIT]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: call void @llvm.aarch64.dmb(i32 10)
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; CHECK-NEXT: ret void
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;
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entry:
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br i1 %f, label %bb_t, label %bb_f
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bb_t:
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call void @llvm.aarch64.dmb(i32 10)
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br label %exit
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bb_f:
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call void @llvm.aarch64.dmb(i32 10)
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br label %exit
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exit:
136+
call void @llvm.aarch64.dmb(i32 10)
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ret void
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}
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140+
define void @multiple_bbs2(i1 %f) #0 {
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; CHECK-LABEL: define void @multiple_bbs2(
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; CHECK-SAME: i1 [[F:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br i1 [[F]], label %[[BB_T:.*]], label %[[BB_F:.*]]
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; CHECK: [[BB_T]]:
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; CHECK-NEXT: br label %[[EXIT:.*]]
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; CHECK: [[BB_F]]:
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; CHECK-NEXT: br label %[[EXIT]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: call void @llvm.aarch64.dmb(i32 10)
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; CHECK-NEXT: ret void
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;
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entry:
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br i1 %f, label %bb_t, label %bb_f
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bb_t:
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call void @llvm.aarch64.dmb(i32 10)
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br label %exit
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bb_f:
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br label %exit
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exit:
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call void @llvm.aarch64.dmb(i32 10)
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ret void
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}
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define void @multiple_bbs3(i1 %f, ptr %p) #0 {
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; CHECK-LABEL: define void @multiple_bbs3(
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; CHECK-SAME: i1 [[F:%.*]], ptr [[P:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br i1 [[F]], label %[[BB_T:.*]], label %[[BB_F:.*]]
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; CHECK: [[BB_T]]:
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; CHECK-NEXT: br label %[[EXIT:.*]]
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; CHECK: [[BB_F]]:
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; CHECK-NEXT: store i32 42, ptr [[P]], align 4
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; CHECK-NEXT: br label %[[EXIT]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: call void @llvm.aarch64.dmb(i32 10)
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; CHECK-NEXT: ret void
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;
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entry:
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br i1 %f, label %bb_t, label %bb_f
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bb_t:
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call void @llvm.aarch64.dmb(i32 10)
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br label %exit
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bb_f:
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store i32 42, ptr %p
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br label %exit
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exit:
188+
call void @llvm.aarch64.dmb(i32 10)
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ret void
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}
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define void @multiple_bbs_unsafe(i1 %f, ptr %p) #0 {
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; CHECK-LABEL: define void @multiple_bbs_unsafe(
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; CHECK-SAME: i1 [[F:%.*]], ptr [[P:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br i1 [[F]], label %[[BB_T:.*]], label %[[BB_F:.*]]
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; CHECK: [[BB_T]]:
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; CHECK-NEXT: call void @llvm.aarch64.dmb(i32 10)
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; CHECK-NEXT: store i32 42, ptr [[P]], align 4
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; CHECK-NEXT: br label %[[EXIT:.*]]
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; CHECK: [[BB_F]]:
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; CHECK-NEXT: br label %[[EXIT]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: call void @llvm.aarch64.dmb(i32 10)
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; CHECK-NEXT: ret void
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;
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entry:
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br i1 %f, label %bb_t, label %bb_f
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bb_t:
210+
call void @llvm.aarch64.dmb(i32 10)
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store i32 42, ptr %p
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br label %exit
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bb_f:
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call void @llvm.aarch64.dmb(i32 10)
215+
br label %exit
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exit:
217+
call void @llvm.aarch64.dmb(i32 10)
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ret void
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}
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