TRAP prefix vs bb name conflict

Created using spr 1.3.4

Author: vitalybuka

llvm/test/Instrumentation/BoundsChecking/runtimes.ll

@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
-; RUN: opt < %s -passes=bounds-checking                 -S | FileCheck %s --check-prefixes=TRAP
-; RUN: opt < %s -passes='bounds-checking<trap>'         -S | FileCheck %s --check-prefixes=TRAP
+; RUN: opt < %s -passes=bounds-checking                 -S | FileCheck %s --check-prefixes=TR
+; RUN: opt < %s -passes='bounds-checking<trap>'         -S | FileCheck %s --check-prefixes=TR
 ; RUN: opt < %s -passes='bounds-checking<rt>'           -S | FileCheck %s --check-prefixes=RT
 ; RUN: opt < %s -passes='bounds-checking<rt-abort>'     -S | FileCheck %s --check-prefixes=RTABORT
 ; RUN: opt < %s -passes='bounds-checking<min-rt>'       -S | FileCheck %s --check-prefixes=MINRT
@@ -9,81 +9,81 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 
 define void @f1(i64 %x) nounwind {
-; TRAP-LABEL: define void @f1(
-; TRAP-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
-; TRAP-NEXT:    [[TMP7:%.*]] = mul i64 16, [[X]]
-; TRAP-NEXT:    [[TMP1:%.*]] = alloca i128, i64 [[X]], align 8
-; TRAP-NEXT:    [[TMP3:%.*]] = sub i64 [[TMP7]], 0
-; TRAP-NEXT:    [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16
-; TRAP-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP4]]
-; TRAP-NEXT:    [[TMP6:%.*]] = or i1 false, [[TMP5]]
-; TRAP-NEXT:    br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]]
-; TRAP:       [[BB7]]:
-; TRAP-NEXT:    [[TMP2:%.*]] = load i128, ptr [[TMP1]], align 4
-; TRAP-NEXT:    ret void
-; TRAP:       [[TRAP]]:
-; TRAP-NEXT:    call void @llvm.trap() #[[ATTR2:[0-9]+]]
-; TRAP-NEXT:    unreachable
+; TR-LABEL: define void @f1(
+; TR-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
+; TR-NEXT:    [[TMP1:%.*]] = mul i64 16, [[X]]
+; TR-NEXT:    [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8
+; TR-NEXT:    [[TMP3:%.*]] = sub i64 [[TMP1]], 0
+; TR-NEXT:    [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16
+; TR-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP4]]
+; TR-NEXT:    [[TMP6:%.*]] = or i1 false, [[TMP5]]
+; TR-NEXT:    br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]]
+; TR:       [[BB7]]:
+; TR-NEXT:    [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4
+; TR-NEXT:    ret void
+; TR:       [[TRAP]]:
+; TR-NEXT:    call void @llvm.trap() #[[ATTR2:[0-9]+]]
+; TR-NEXT:    unreachable
 ;
 ; RT-LABEL: define void @f1(
 ; RT-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
-; RT-NEXT:    [[TMP7:%.*]] = mul i64 16, [[X]]
-; RT-NEXT:    [[TMP1:%.*]] = alloca i128, i64 [[X]], align 8
-; RT-NEXT:    [[TMP3:%.*]] = sub i64 [[TMP7]], 0
+; RT-NEXT:    [[TMP1:%.*]] = mul i64 16, [[X]]
+; RT-NEXT:    [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8
+; RT-NEXT:    [[TMP3:%.*]] = sub i64 [[TMP1]], 0
 ; RT-NEXT:    [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16
 ; RT-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP4]]
 ; RT-NEXT:    [[TMP6:%.*]] = or i1 false, [[TMP5]]
 ; RT-NEXT:    br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]]
 ; RT:       [[BB7]]:
-; RT-NEXT:    [[TMP2:%.*]] = load i128, ptr [[TMP1]], align 4
+; RT-NEXT:    [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4
 ; RT-NEXT:    ret void
 ; RT:       [[TRAP]]:
 ; RT-NEXT:    call void @llvm.trap() #[[ATTR2:[0-9]+]]
 ; RT-NEXT:    unreachable
 ;
 ; RTABORT-LABEL: define void @f1(
 ; RTABORT-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
-; RTABORT-NEXT:    [[TMP7:%.*]] = mul i64 16, [[X]]
-; RTABORT-NEXT:    [[TMP1:%.*]] = alloca i128, i64 [[X]], align 8
-; RTABORT-NEXT:    [[TMP3:%.*]] = sub i64 [[TMP7]], 0
+; RTABORT-NEXT:    [[TMP1:%.*]] = mul i64 16, [[X]]
+; RTABORT-NEXT:    [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8
+; RTABORT-NEXT:    [[TMP3:%.*]] = sub i64 [[TMP1]], 0
 ; RTABORT-NEXT:    [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16
 ; RTABORT-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP4]]
 ; RTABORT-NEXT:    [[TMP6:%.*]] = or i1 false, [[TMP5]]
 ; RTABORT-NEXT:    br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]]
 ; RTABORT:       [[BB7]]:
-; RTABORT-NEXT:    [[TMP2:%.*]] = load i128, ptr [[TMP1]], align 4
+; RTABORT-NEXT:    [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4
 ; RTABORT-NEXT:    ret void
 ; RTABORT:       [[TRAP]]:
 ; RTABORT-NEXT:    call void @llvm.trap() #[[ATTR2:[0-9]+]]
 ; RTABORT-NEXT:    unreachable
 ;
 ; MINRT-LABEL: define void @f1(
 ; MINRT-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
-; MINRT-NEXT:    [[TMP7:%.*]] = mul i64 16, [[X]]
-; MINRT-NEXT:    [[TMP1:%.*]] = alloca i128, i64 [[X]], align 8
-; MINRT-NEXT:    [[TMP3:%.*]] = sub i64 [[TMP7]], 0
+; MINRT-NEXT:    [[TMP1:%.*]] = mul i64 16, [[X]]
+; MINRT-NEXT:    [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8
+; MINRT-NEXT:    [[TMP3:%.*]] = sub i64 [[TMP1]], 0
 ; MINRT-NEXT:    [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16
 ; MINRT-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP4]]
 ; MINRT-NEXT:    [[TMP6:%.*]] = or i1 false, [[TMP5]]
 ; MINRT-NEXT:    br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]]
 ; MINRT:       [[BB7]]:
-; MINRT-NEXT:    [[TMP2:%.*]] = load i128, ptr [[TMP1]], align 4
+; MINRT-NEXT:    [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4
 ; MINRT-NEXT:    ret void
 ; MINRT:       [[TRAP]]:
 ; MINRT-NEXT:    call void @llvm.trap() #[[ATTR2:[0-9]+]]
 ; MINRT-NEXT:    unreachable
 ;
 ; MINRTABORT-LABEL: define void @f1(
 ; MINRTABORT-SAME: i64 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
-; MINRTABORT-NEXT:    [[TMP7:%.*]] = mul i64 16, [[X]]
-; MINRTABORT-NEXT:    [[TMP1:%.*]] = alloca i128, i64 [[X]], align 8
-; MINRTABORT-NEXT:    [[TMP3:%.*]] = sub i64 [[TMP7]], 0
+; MINRTABORT-NEXT:    [[TMP1:%.*]] = mul i64 16, [[X]]
+; MINRTABORT-NEXT:    [[TMP2:%.*]] = alloca i128, i64 [[X]], align 8
+; MINRTABORT-NEXT:    [[TMP3:%.*]] = sub i64 [[TMP1]], 0
 ; MINRTABORT-NEXT:    [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 16
 ; MINRTABORT-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP4]]
 ; MINRTABORT-NEXT:    [[TMP6:%.*]] = or i1 false, [[TMP5]]
 ; MINRTABORT-NEXT:    br i1 [[TMP6]], label %[[TRAP:.*]], label %[[BB7:.*]]
 ; MINRTABORT:       [[BB7]]:
-; MINRTABORT-NEXT:    [[TMP2:%.*]] = load i128, ptr [[TMP1]], align 4
+; MINRTABORT-NEXT:    [[TMP8:%.*]] = load i128, ptr [[TMP2]], align 4
 ; MINRTABORT-NEXT:    ret void
 ; MINRTABORT:       [[TRAP]]:
 ; MINRTABORT-NEXT:    call void @llvm.trap() #[[ATTR2:[0-9]+]]