review comments

    - add check for "convergencectrl" token in hlsl -> spirv intrinsic
    - correct the execution scope of the spirv instruction, add
      description
    - fix typo

Author: inbelic

clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl

@@ -11,7 +11,7 @@
 int test_int(int expr, uint idx) {
   // CHECK-SPIRV: %[[#entry_tok:]] = call token @llvm.experimental.convergence.entry()
 
-  // CHECK-SPIRV:  %[[RET:.*]] = call [[TY:.*]] @llvm.spv.wave.read.lane.at.i32([[TY]] %[[#]], i32 %[[#]])
+  // CHECK-SPIRV:  %[[RET:.*]] = call [[TY:.*]] @llvm.spv.wave.read.lane.at.i32([[TY]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok]]) ]
   // CHECK-DXIL:  %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.read.lane.at.i32([[TY]] %[[#]], i32 %[[#]])
 
   // CHECK:  ret [[TY]] %[[RET]]
@@ -27,7 +27,7 @@ int test_int(int expr, uint idx) {
 float4 test_floatv4(float4 expr, uint idx) {
   // CHECK-SPIRV: %[[#entry_tok1:]] = call token @llvm.experimental.convergence.entry()
 
-  // CHECK-SPIRV:  %[[RET1:.*]] = call [[TY1:.*]] @llvm.spv.wave.read.lane.at.v4f32([[TY1]] %[[#]], i32 %[[#]])
+  // CHECK-SPIRV:  %[[RET1:.*]] = call [[TY1:.*]] @llvm.spv.wave.read.lane.at.v4f32([[TY1]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok1]]) ]
   // CHECK-DXIL:  %[[RET1:.*]] = call [[TY1:.*]] @llvm.dx.wave.read.lane.at.v4f32([[TY1]] %[[#]], i32 %[[#]])
 
   // CHECK:  ret [[TY1]] %[[RET1]]

llvm/lib/Target/DirectX/DXIL.td

@@ -802,7 +802,7 @@ def WaveIsFirstLane :  DXILOp<110, waveIsFirstLane> {
   let attributes = [Attributes<DXIL1_0, [ReadNone]>];
 }
 
-def WaveReadLaneAt:  DXILOp<117, waveIsFirstLane> {
+def WaveReadLaneAt:  DXILOp<117, waveReadLaneAt> {
   let Doc = "returns the value from the specified lane";
   let LLVMIntrinsic = int_dx_wave_read_lane_at;
   let arguments = [OverloadTy, Int32Ty];

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

@@ -2658,15 +2658,16 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
     assert(I.getOperand(2).isReg());
     assert(I.getOperand(3).isReg());
 
-    // Defines the execution scope currently 2 for group, see scope table
+    // IntTy is used to define the execution scope, set to 3 to denote a
+    // cross-lane interaction equivalent to a SPIR-V subgroup.
     SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
     return BuildMI(BB, I, I.getDebugLoc(),
                    TII.get(SPIRV::OpGroupNonUniformShuffle))
         .addDef(ResVReg)
         .addUse(GR.getSPIRVTypeID(ResType))
         .addUse(I.getOperand(2).getReg())
         .addUse(I.getOperand(3).getReg())
-        .addUse(GR.getOrCreateConstInt(2, I, IntTy, TII));
+        .addUse(GR.getOrCreateConstInt(3, I, IntTy, TII));
   }
   case Intrinsic::spv_step:
     return selectStep(ResVReg, ResType, I);

llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll

@@ -4,7 +4,7 @@
 ; Test lowering to spir-v backend
 
 ; CHECK-DAG:   %[[#uint:]] = OpTypeInt 32 0
-; CHECK-DAG:   %[[#scope:]] = OpConstant %[[#uint]] 2
+; CHECK-DAG:   %[[#scope:]] = OpConstant %[[#uint]] 3
 ; CHECK-DAG:   %[[#f32:]] = OpTypeFloat 32
 ; CHECK-DAG:   %[[#expr:]] = OpFunctionParameter %[[#f32]]
 ; CHECK-DAG:   %[[#idx:]] = OpFunctionParameter %[[#uint]]