Response to review comments addressing:

- check for scalar type
- check for sign extends
- legalise vector inputs to sqdmulh
- always return sext(sqdmulh)

Change-Id: Ic58b7f267e94bc2592942fc29b829ffb6221770f

Author: nasherm

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -21005,9 +21005,9 @@ static SDValue trySQDMULHCombine(SDNode *N, SelectionDAG &DAG) {
   if (N->getOpcode() != ISD::SMIN)
     return SDValue();
 
-  EVT VT = N->getValueType(0);
+  EVT DestVT = N->getValueType(0);
 
-  if (!VT.isVector() || VT.getScalarSizeInBits() > 64)
+  if (!DestVT.isVector() || DestVT.getScalarSizeInBits() > 64 || DestVT.isScalableVector())
     return SDValue();
 
   ConstantSDNode *Clamp = isConstOrConstSplat(N->getOperand(1));
@@ -21049,28 +21049,36 @@ static SDValue trySQDMULHCombine(SDNode *N, SelectionDAG &DAG) {
   SDValue SExt0 = Mul.getOperand(0);
   SDValue SExt1 = Mul.getOperand(1);
 
+  if (SExt0.getOpcode() != ISD::SIGN_EXTEND ||
+      SExt1.getOpcode() != ISD::SIGN_EXTEND)
+    return SDValue();
+
   EVT SExt0Type = SExt0.getOperand(0).getValueType();
   EVT SExt1Type = SExt1.getOperand(0).getValueType();
 
-  if (SExt0.getOpcode() != ISD::SIGN_EXTEND ||
-      SExt1.getOpcode() != ISD::SIGN_EXTEND || SExt0Type != SExt1Type ||
+  if (SExt0Type != SExt1Type ||
       SExt0Type.getScalarType() != ScalarType ||
       SExt0Type.getFixedSizeInBits() > 128)
     return SDValue();
 
-  // Source vectors with width < 64 are illegal and will need to be extended
-  unsigned SourceVectorWidth = SExt0Type.getFixedSizeInBits();
-  SDValue V0 = (SourceVectorWidth < 64) ? SExt0 : SExt0.getOperand(0);
-  SDValue V1 = (SourceVectorWidth < 64) ? SExt1 : SExt1.getOperand(0);
-
   SDLoc DL(N);
+  SDValue V0 = SExt0.getOperand(0);
+  SDValue V1 = SExt1.getOperand(0);
+
+  // Ensure input vectors are extended to legal types
+  if (SExt0Type.getFixedSizeInBits() < 64) {
+      unsigned VecNumElements = SExt0Type.getVectorNumElements();
+      EVT ExtVecVT =
+        MVT::getVectorVT(MVT::getIntegerVT(64 / VecNumElements),
+                         VecNumElements);
+    V0 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVecVT, V0);
+    V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVecVT, V1);
+  }
+
   SDValue SQDMULH =
       DAG.getNode(AArch64ISD::SQDMULH, DL, V0.getValueType(), V0, V1);
-  EVT DestVT = N->getValueType(0);
-  if (DestVT.getScalarSizeInBits() > SExt0Type.getScalarSizeInBits())
-    return DAG.getNode(ISD::SIGN_EXTEND, DL, DestVT, SQDMULH);
 
-  return SQDMULH;
+  return DAG.getNode(ISD::SIGN_EXTEND, DL, DestVT, SQDMULH);
 }
 
 static SDValue performSMINCombine(SDNode *N, SelectionDAG &DAG) {

llvm/test/CodeGen/AArch64/saturating-vec-smull.ll

@@ -140,3 +140,43 @@ define <4 x i16> @unsupported_shift_value_v4i16(<4 x i16> %a, <4 x i16> %b) {
   %t = trunc <4 x i32> %ma to <4 x i16>
   ret <4 x i16> %t
 }
+
+define <2 x i16> @extend_to_illegal_type(<2 x i16> %a, <2 x i16> %b) {
+; CHECK-LABEL: extend_to_illegal_type:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    shl v0.2s, v0.2s, #16
+; CHECK-NEXT:    shl v1.2s, v1.2s, #16
+; CHECK-NEXT:    sshr v0.2s, v0.2s, #16
+; CHECK-NEXT:    sshr v1.2s, v1.2s, #16
+; CHECK-NEXT:    sqdmulh v0.2s, v1.2s, v0.2s
+; CHECK-NEXT:    ret
+  %as = sext <2 x i16> %a to <2 x i48>
+  %bs = sext <2 x i16> %b to <2 x i48>
+  %m = mul <2 x i48> %bs, %as
+  %sh = ashr <2 x i48> %m, splat (i48 15)
+  %ma = tail call <2 x i48> @llvm.smin.v4i32(<2 x i48> %sh, <2 x i48> splat (i48 32767))
+  %t = trunc <2 x i48> %ma to <2 x i16>
+  ret <2 x i16> %t
+}
+
+define <2 x i11> @illegal_source(<2 x i11> %a, <2 x i11> %b) {
+; CHECK-LABEL: source_is_illegal:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    shl v0.2s, v0.2s, #21
+; CHECK-NEXT:    shl v1.2s, v1.2s, #21
+; CHECK-NEXT:    sshr v0.2s, v0.2s, #21
+; CHECK-NEXT:    sshr v1.2s, v1.2s, #21
+; CHECK-NEXT:    mul v0.2s, v1.2s, v0.2s
+; CHECK-NEXT:    movi v1.2s, #127, msl #8
+; CHECK-NEXT:    sshr v0.2s, v0.2s, #15
+; CHECK-NEXT:    smin v0.2s, v0.2s, v1.2s
+; CHECK-NEXT:    ret
+  %as = sext <2 x i11> %a to <2 x i32>
+  %bs = sext <2 x i11> %b to <2 x i32>
+  %m = mul <2 x i32> %bs, %as
+  %sh = ashr <2 x i32> %m, splat (i32 15)
+  %ma = tail call <2 x i32> @llvm.smin.v4i32(<2 x i32> %sh, <2 x i32> splat (i32 32767))
+  %t = trunc <2 x i32> %ma to <2 x i11>
+  ret <2 x i11> %t
+}
+