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mshockwavemshockwave
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fixup! Add more tests for factor of 7 and 8
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‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll‎

Lines changed: 71 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1431,6 +1431,40 @@ define void @store_factor6(ptr %ptr, <2 x i16> %v0, <2 x i16> %v1, <2 x i16> %v2
14311431
ret void
14321432
}
14331433

1434+
define void @store_factor7(ptr %ptr, <2 x i16> %v0, <2 x i16> %v1, <2 x i16> %v2, <2 x i16> %v3, <2 x i16> %v4, <2 x i16> %v5, <2 x i16> %v6) {
1435+
; CHECK-LABEL: store_factor7:
1436+
; CHECK: # %bb.0:
1437+
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
1438+
; CHECK-NEXT: vsseg7e16.v v8, (a0)
1439+
; CHECK-NEXT: ret
1440+
%s0 = shufflevector <2 x i16> %v0, <2 x i16> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1441+
%s1 = shufflevector <2 x i16> %v2, <2 x i16> %v3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1442+
%s2 = shufflevector <2 x i16> %v4, <2 x i16> %v5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1443+
%s3 = shufflevector <4 x i16> %s0, <4 x i16> %s1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
1444+
%s4 = shufflevector <2 x i16> %v6, <2 x i16> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
1445+
%s5 = shufflevector <4 x i16> %s2, <4 x i16> %s4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 undef, i32 undef>
1446+
%interleaved.vec = shufflevector <8 x i16> %s3, <8 x i16> %s5, <14 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13>
1447+
store <14 x i16> %interleaved.vec, ptr %ptr
1448+
ret void
1449+
}
1450+
1451+
define void @store_factor8(ptr %ptr, <2 x i16> %v0, <2 x i16> %v1, <2 x i16> %v2, <2 x i16> %v3, <2 x i16> %v4, <2 x i16> %v5, <2 x i16> %v6, <2 x i16> %v7) {
1452+
; CHECK-LABEL: store_factor8:
1453+
; CHECK: # %bb.0:
1454+
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
1455+
; CHECK-NEXT: vsseg8e16.v v8, (a0)
1456+
; CHECK-NEXT: ret
1457+
%s0 = shufflevector <2 x i16> %v0, <2 x i16> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1458+
%s1 = shufflevector <2 x i16> %v2, <2 x i16> %v3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1459+
%s2 = shufflevector <2 x i16> %v4, <2 x i16> %v5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1460+
%s3 = shufflevector <4 x i16> %s0, <4 x i16> %s1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
1461+
%s4 = shufflevector <2 x i16> %v6, <2 x i16> %v7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1462+
%s5 = shufflevector <4 x i16> %s2, <4 x i16> %s4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
1463+
%interleaved.vec = shufflevector <8 x i16> %s3, <8 x i16> %s5, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
1464+
store <16 x i16> %interleaved.vec, ptr %ptr
1465+
ret void
1466+
}
1467+
14341468
define void @vpstore_factor2(ptr %ptr, <4 x i32> %v0, <4 x i32> %v1) {
14351469
; CHECK-LABEL: vpstore_factor2:
14361470
; CHECK: # %bb.0:
@@ -1512,6 +1546,39 @@ define void @vpstore_factor6(ptr %ptr, <2 x i16> %v0, <2 x i16> %v1, <2 x i16> %
15121546
ret void
15131547
}
15141548

1549+
define void @vpstore_factor7(ptr %ptr, <2 x i16> %v0, <2 x i16> %v1, <2 x i16> %v2, <2 x i16> %v3, <2 x i16> %v4, <2 x i16> %v5, <2 x i16> %v6) {
1550+
; CHECK-LABEL: vpstore_factor7:
1551+
; CHECK: # %bb.0:
1552+
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
1553+
; CHECK-NEXT: vsseg7e16.v v8, (a0)
1554+
; CHECK-NEXT: ret
1555+
%s0 = shufflevector <2 x i16> %v0, <2 x i16> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1556+
%s1 = shufflevector <2 x i16> %v2, <2 x i16> %v3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1557+
%s2 = shufflevector <2 x i16> %v4, <2 x i16> %v5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1558+
%s3 = shufflevector <4 x i16> %s0, <4 x i16> %s1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
1559+
%s4 = shufflevector <2 x i16> %v6, <2 x i16> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
1560+
%s5 = shufflevector <4 x i16> %s2, <4 x i16> %s4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 undef, i32 undef>
1561+
%interleaved.vec = shufflevector <8 x i16> %s3, <8 x i16> %s5, <14 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13>
1562+
tail call void @llvm.vp.store.v14i16.p0(<14 x i16> %interleaved.vec, ptr %ptr, <14 x i1> splat (i1 true), i32 14)
1563+
ret void
1564+
}
1565+
1566+
define void @vpstore_factor8(ptr %ptr, <2 x i16> %v0, <2 x i16> %v1, <2 x i16> %v2, <2 x i16> %v3, <2 x i16> %v4, <2 x i16> %v5, <2 x i16> %v6, <2 x i16> %v7) {
1567+
; CHECK-LABEL: vpstore_factor8:
1568+
; CHECK: # %bb.0:
1569+
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
1570+
; CHECK-NEXT: vsseg8e16.v v8, (a0)
1571+
; CHECK-NEXT: ret
1572+
%s0 = shufflevector <2 x i16> %v0, <2 x i16> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1573+
%s1 = shufflevector <2 x i16> %v2, <2 x i16> %v3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1574+
%s2 = shufflevector <2 x i16> %v4, <2 x i16> %v5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1575+
%s3 = shufflevector <4 x i16> %s0, <4 x i16> %s1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
1576+
%s4 = shufflevector <2 x i16> %v6, <2 x i16> %v7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1577+
%s5 = shufflevector <4 x i16> %s2, <4 x i16> %s4, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
1578+
%interleaved.vec = shufflevector <8 x i16> %s3, <8 x i16> %s5, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
1579+
tail call void @llvm.vp.store.v16i16.p0(<16 x i16> %interleaved.vec, ptr %ptr, <16 x i1> splat (i1 true), i32 16)
1580+
ret void
1581+
}
15151582

15161583
define <4 x i32> @load_factor2_one_active(ptr %ptr) {
15171584
; CHECK-LABEL: load_factor2_one_active:
@@ -1703,8 +1770,8 @@ define {<4 x i32>, <4 x i32>, <4 x i32>} @invalid_vp_mask(ptr %ptr) {
17031770
; RV32-NEXT: vle32.v v12, (a0), v0.t
17041771
; RV32-NEXT: li a0, 36
17051772
; RV32-NEXT: vmv.s.x v20, a1
1706-
; RV32-NEXT: lui a1, %hi(.LCPI45_0)
1707-
; RV32-NEXT: addi a1, a1, %lo(.LCPI45_0)
1773+
; RV32-NEXT: lui a1, %hi(.LCPI49_0)
1774+
; RV32-NEXT: addi a1, a1, %lo(.LCPI49_0)
17081775
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
17091776
; RV32-NEXT: vle16.v v21, (a1)
17101777
; RV32-NEXT: vcompress.vm v8, v12, v11
@@ -1779,8 +1846,8 @@ define {<4 x i32>, <4 x i32>, <4 x i32>} @invalid_vp_evl(ptr %ptr) {
17791846
; RV32-NEXT: vmv.s.x v10, a0
17801847
; RV32-NEXT: li a0, 146
17811848
; RV32-NEXT: vmv.s.x v11, a0
1782-
; RV32-NEXT: lui a0, %hi(.LCPI46_0)
1783-
; RV32-NEXT: addi a0, a0, %lo(.LCPI46_0)
1849+
; RV32-NEXT: lui a0, %hi(.LCPI50_0)
1850+
; RV32-NEXT: addi a0, a0, %lo(.LCPI50_0)
17841851
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
17851852
; RV32-NEXT: vle16.v v20, (a0)
17861853
; RV32-NEXT: li a0, 36

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