Skip to content

Commit 1c2072f

Browse files
committed
[AMDGPU] Fix AGPR_32 reg assign for mfma scale ops
In MFMA rewrite pass, prevent AGPR_32 reg class assignment for scale operands, not permitted by instruction format.
1 parent 76d614b commit 1c2072f

File tree

2 files changed

+7
-3
lines changed

2 files changed

+7
-3
lines changed

llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -302,6 +302,10 @@ bool AMDGPURewriteAGPRCopyMFMAImpl::attemptReassignmentsToAGPR(
302302
const TargetRegisterClass *EquivalentAGPRRegClass =
303303
TRI.getEquivalentAGPRClass(MRI.getRegClass(InterferingReg));
304304

305+
// Do not reassign scale operands
306+
if (EquivalentAGPRRegClass == &AMDGPU::AGPR_32RegClass)
307+
return false;
308+
305309
MCPhysReg Assignable = AMDGPU::NoRegister;
306310
if (EquivalentAGPRRegClass->contains(PrefPhysReg) &&
307311
LRM.checkInterference(ReassignLI, PrefPhysReg) ==

llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-scale-to-agpr.mir

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
1-
# RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -run-pass=greedy,amdgpu-rewrite-agpr-copy-mfma -verify-machineinstrs -o - %s 2>&1 | FileCheck %s
2-
# CHECK: Illegal virtual register for instruction
3-
# CHECK: Expected a VGPR_32 register, but got a AGPR_32 register
1+
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -run-pass=greedy,amdgpu-rewrite-agpr-copy-mfma -verify-machineinstrs -o - %s 2>&1 | FileCheck %s
2+
# CHECK-NOT: Illegal virtual register for instruction
3+
# CHECK-NOT: Expected a VGPR_32 register, but got a AGPR_32 register
44

55
# Test for issue in amdgpu-rewrite-agpr-copy-mfma, which reassigns scale operand
66
# in vgpr_32 register to agpr_32, not permitted by instruction format.

0 commit comments

Comments
 (0)