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[LoongArch] Add support for vector FP_ROUND from vxf64 to vxf32
In LoongArch, [x]vfcvt.s.d intstructions require two vector registers for v4f64->v4f32, v8f64->v8f32 conversions. This patch handles these cases: - For FP_ROUND v2f64->v2f32(illegal), add a customized v2f32 widening to convert it into a target-specific LoongArchISD::VFCVT. - For FP_ROUND v4f64->v4f32, on LSX platforms, v4f64 is illegal and will be split into two v2f64->v2f32, resulting in two LoongArchISD::VFCVT. Finally, they are combined into a single node during combining LoongArchISD::VPACKEV. On LASX platforms, v4f64->v4f32 can directly lower to vfcvt.s.d in lowerFP_ROUND. - For FP_ROUND v8f64->v8f32, on LASX platforms, v8f64 is illegal and will be split into two v4f64->v4f32 and then combine using ISD::CONCAT_VECTORS, so xvfcvt.s.d is generated during its combination.
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‎llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp‎

Lines changed: 135 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -386,6 +386,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
386386
setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
387387
setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
388388
}
389+
setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
389390
}
390391

391392
// Set operations for 'LASX' feature.
@@ -448,6 +449,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
448449
VT, Expand);
449450
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
450451
}
452+
setOperationAction(ISD::FP_ROUND, MVT::v4f32, Custom);
451453
}
452454

453455
// Set DAG combine for LA32 and LA64.
@@ -466,8 +468,10 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
466468

467469
// Set DAG combine for 'LASX' feature.
468470

469-
if (Subtarget.hasExtLASX())
471+
if (Subtarget.hasExtLASX()) {
470472
setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
473+
setTargetDAGCombine(ISD::CONCAT_VECTORS);
474+
}
471475

472476
// Compute derived properties from the register classes.
473477
computeRegisterProperties(Subtarget.getRegisterInfo());
@@ -592,7 +596,101 @@ SDValue LoongArchTargetLowering::LowerOperation(SDValue Op,
592596
return lowerVECREDUCE(Op, DAG);
593597
case ISD::ConstantFP:
594598
return lowerConstantFP(Op, DAG);
599+
case ISD::FP_ROUND:
600+
return lowerFP_ROUND(Op, DAG);
601+
}
602+
return SDValue();
603+
}
604+
605+
// Combine two ISD::FP_ROUND / LoongArchISD::VFCVT nodes with same type to
606+
// LoongArchISD::VFCVT. For example:
607+
// x1 = fp_round x, 0
608+
// y1 = fp_round y, 0
609+
// z = concat_vectors x1, y1
610+
// Or
611+
// x1 = LoongArch::VFCVT undef, x
612+
// y1 = LoongArch::VFCVT undef, y
613+
// z = LoongArchISD::VPACKEV y1, x1
614+
// can be combined to:
615+
// z = LoongArch::VFCVT y, x
616+
static SDValue combineFP_ROUND(SDValue N, const SDLoc &DL, SelectionDAG &DAG,
617+
const LoongArchSubtarget &Subtarget) {
618+
assert(((N->getOpcode() == ISD::CONCAT_VECTORS && N->getNumOperands() == 2) ||
619+
(N->getOpcode() == LoongArchISD::VPACKEV)) &&
620+
"Invalid Node");
621+
622+
SDValue Op0 = peekThroughBitcasts(N->getOperand(0));
623+
SDValue Op1 = peekThroughBitcasts(N->getOperand(1));
624+
unsigned Opcode0 = Op0.getOpcode();
625+
unsigned Opcode1 = Op1.getOpcode();
626+
if (Opcode0 != Opcode1)
627+
return SDValue();
628+
629+
if (Opcode0 != ISD::FP_ROUND && Opcode0 != LoongArchISD::VFCVT)
630+
return SDValue();
631+
632+
// Check if two nodes have only one use.
633+
if (!Op0.hasOneUse() || !Op1.hasOneUse())
634+
return SDValue();
635+
636+
EVT VT = N.getValueType();
637+
EVT SVT0 = Op0.getValueType();
638+
EVT SVT1 = Op1.getValueType();
639+
// Check if two nodes have the same result type.
640+
if (SVT0 != SVT1)
641+
return SDValue();
642+
643+
// Check if two nodes have the same operand type.
644+
EVT SSVT0 = Op0.getOperand(0).getValueType();
645+
EVT SSVT1 = Op1.getOperand(0).getValueType();
646+
if (SSVT0 != SSVT1)
647+
return SDValue();
648+
649+
if (N->getOpcode() == ISD::CONCAT_VECTORS && Opcode0 == ISD::FP_ROUND) {
650+
if (Subtarget.hasExtLASX() && VT.is256BitVector() && SVT0 == MVT::v4f32 &&
651+
SSVT0 == MVT::v4f64) {
652+
// A vector_shuffle is required in the final step, as xvfcvt instruction
653+
// operates on each 128-bit segament as a lane.
654+
SDValue Res = DAG.getNode(LoongArchISD::VFCVT, DL, MVT::v8f32,
655+
Op1.getOperand(0), Op0.getOperand(0));
656+
SDValue Undef = DAG.getUNDEF(VT);
657+
SmallVector<int, 8> Mask = {0, 1, 4, 5, 2, 3, 6, 7};
658+
Res = DAG.getVectorShuffle(VT, DL, Res, Undef, Mask);
659+
return DAG.getBitcast(VT, Res);
660+
}
595661
}
662+
663+
if (N->getOpcode() == LoongArchISD::VPACKEV &&
664+
Opcode0 == LoongArchISD::VFCVT) {
665+
// For VPACKEV, check if the first operation of LoongArchISD::VFCVT is
666+
// undef.
667+
if (!Op0.getOperand(0).isUndef() || !Op1.getOperand(0).isUndef())
668+
return SDValue();
669+
670+
if (Subtarget.hasExtLSX() && (VT == MVT::v2i64 || VT == MVT::v2f64) &&
671+
SVT0 == MVT::v4f32 && SSVT0 == MVT::v2f64) {
672+
SDValue Res = DAG.getNode(LoongArchISD::VFCVT, DL, MVT::v4f32,
673+
Op0.getOperand(1), Op1.getOperand(1));
674+
return DAG.getBitcast(VT, Res);
675+
}
676+
}
677+
678+
return SDValue();
679+
}
680+
681+
SDValue LoongArchTargetLowering::lowerFP_ROUND(SDValue Op,
682+
SelectionDAG &DAG) const {
683+
SDLoc DL(Op);
684+
SDValue In = Op.getOperand(0);
685+
MVT VT = Op.getSimpleValueType();
686+
MVT SVT = In.getSimpleValueType();
687+
688+
if (VT == MVT::v4f32 && SVT == MVT::v4f64) {
689+
SDValue Lo, Hi;
690+
std::tie(Lo, Hi) = DAG.SplitVector(In, DL);
691+
return DAG.getNode(LoongArchISD::VFCVT, DL, VT, Hi, Lo);
692+
}
693+
596694
return SDValue();
597695
}
598696

@@ -4720,6 +4818,21 @@ void LoongArchTargetLowering::ReplaceNodeResults(
47204818
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Tmp1));
47214819
break;
47224820
}
4821+
case ISD::FP_ROUND: {
4822+
assert(VT == MVT::v2f32 && Subtarget.hasExtLSX() &&
4823+
"Unexpected custom legalisation");
4824+
// On LSX platforms, rounding from v2f64 to v4f32 (after legalization from
4825+
// v2f32) is scalarized. Add a customized v2f32 widening to convert it into
4826+
// a target-specific LoongArchISD::VFCVT to optimize it.
4827+
if (VT == MVT::v2f32) {
4828+
SDValue Src = N->getOperand(0);
4829+
SDValue Undef = DAG.getUNDEF(Src.getValueType());
4830+
SDValue Dst =
4831+
DAG.getNode(LoongArchISD::VFCVT, DL, MVT::v4f32, Undef, Src);
4832+
Results.push_back(Dst);
4833+
}
4834+
break;
4835+
}
47234836
case ISD::BSWAP: {
47244837
SDValue Src = N->getOperand(0);
47254838
assert((VT == MVT::i16 || VT == MVT::i32) &&
@@ -6679,6 +6792,20 @@ performEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
66796792
return SDValue();
66806793
}
66816794

6795+
static SDValue
6796+
performCONCAT_VECTORSCombine(SDNode *N, SelectionDAG &DAG,
6797+
TargetLowering::DAGCombinerInfo &DCI,
6798+
const LoongArchSubtarget &Subtarget) {
6799+
SDLoc DL(N);
6800+
EVT VT = N->getValueType(0);
6801+
6802+
if (VT.isVector() && N->getNumOperands() == 2)
6803+
if (SDValue R = combineFP_ROUND(SDValue(N, 0), DL, DAG, Subtarget))
6804+
return R;
6805+
6806+
return SDValue();
6807+
}
6808+
66826809
SDValue LoongArchTargetLowering::PerformDAGCombine(SDNode *N,
66836810
DAGCombinerInfo &DCI) const {
66846811
SelectionDAG &DAG = DCI.DAG;
@@ -6714,6 +6841,12 @@ SDValue LoongArchTargetLowering::PerformDAGCombine(SDNode *N,
67146841
return performSPLIT_PAIR_F64Combine(N, DAG, DCI, Subtarget);
67156842
case ISD::EXTRACT_VECTOR_ELT:
67166843
return performEXTRACT_VECTOR_ELTCombine(N, DAG, DCI, Subtarget);
6844+
case ISD::CONCAT_VECTORS:
6845+
return performCONCAT_VECTORSCombine(N, DAG, DCI, Subtarget);
6846+
case LoongArchISD::VPACKEV:
6847+
if (SDValue Result =
6848+
combineFP_ROUND(SDValue(N, 0), SDLoc(N), DAG, Subtarget))
6849+
return Result;
67176850
}
67186851
return SDValue();
67196852
}
@@ -7512,6 +7645,7 @@ const char *LoongArchTargetLowering::getTargetNodeName(unsigned Opcode) const {
75127645
NODE_NAME_CASE(VANY_NONZERO)
75137646
NODE_NAME_CASE(FRECIPE)
75147647
NODE_NAME_CASE(FRSQRTE)
7648+
NODE_NAME_CASE(VFCVT)
75157649
NODE_NAME_CASE(VSLLI)
75167650
NODE_NAME_CASE(VSRLI)
75177651
NODE_NAME_CASE(VBSLL)

‎llvm/lib/Target/LoongArch/LoongArchISelLowering.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -167,6 +167,8 @@ enum NodeType : unsigned {
167167
FRECIPE,
168168
FRSQRTE,
169169

170+
VFCVT,
171+
170172
// Vector logicial left / right shift by immediate
171173
VSLLI,
172174
VSRLI,
@@ -415,6 +417,7 @@ class LoongArchTargetLowering : public TargetLowering {
415417
SDValue lowerVECREDUCE_ADD(SDValue Op, SelectionDAG &DAG) const;
416418
SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
417419
SDValue lowerConstantFP(SDValue Op, SelectionDAG &DAG) const;
420+
SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
418421

419422
bool isFPImmLegal(const APFloat &Imm, EVT VT,
420423
bool ForCodeSize) const override;

‎llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2403,6 +2403,10 @@ def : Pat<(int_loongarch_lasx_xvpickve_w_f v8f32:$xj, timm:$imm),
24032403
def : Pat<(int_loongarch_lasx_xvpickve_d_f v4f64:$xj, timm:$imm),
24042404
(XVPICKVE_D v4f64:$xj, (to_valid_timm timm:$imm))>;
24052405

2406+
// Vector floating-point conversion
2407+
def : Pat<(v8f32 (loongarch_vfcvt_s_d (v4f64 LASX256:$xj), (v4f64 LASX256:$xk))),
2408+
(XVFCVT_S_D LASX256:$xj, LASX256:$xk)>;
2409+
24062410
// load
24072411
def : Pat<(int_loongarch_lasx_xvld GPR:$rj, timm:$imm),
24082412
(XVLD GPR:$rj, (to_valid_timm timm:$imm))>;

‎llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,8 @@ def SDT_LoongArchVFRECIPE : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVec<0>, SDTC
3232
def SDT_LoongArchVFRSQRTE : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
3333
def SDT_LoongArchVLDREPL : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisPtrTy<1>]>;
3434
def SDT_LoongArchVMSKCOND : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;
35+
def SDT_LoongArchVFCVT_S_D : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisFP<0>,
36+
SDTCisVec<1>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
3537

3638
// Target nodes.
3739
def loongarch_vreplve : SDNode<"LoongArchISD::VREPLVE", SDT_LoongArchVreplve>;
@@ -82,6 +84,8 @@ def loongarch_vmskgez: SDNode<"LoongArchISD::VMSKGEZ", SDT_LoongArchVMSKCOND>;
8284
def loongarch_vmskeqz: SDNode<"LoongArchISD::VMSKEQZ", SDT_LoongArchVMSKCOND>;
8385
def loongarch_vmsknez: SDNode<"LoongArchISD::VMSKNEZ", SDT_LoongArchVMSKCOND>;
8486

87+
def loongarch_vfcvt_s_d: SDNode<"LoongArchISD::VFCVT", SDT_LoongArchVFCVT_S_D>;
88+
8589
def immZExt1 : ImmLeaf<GRLenVT, [{return isUInt<1>(Imm);}]>;
8690
def immZExt2 : ImmLeaf<GRLenVT, [{return isUInt<2>(Imm);}]>;
8791
def immZExt3 : ImmLeaf<GRLenVT, [{return isUInt<3>(Imm);}]>;
@@ -2519,6 +2523,9 @@ def : Pat<(f64 (froundeven FPR64:$fj)),
25192523
(f64 (EXTRACT_SUBREG (VFRINTRNE_D (VREPLVEI_D
25202524
(SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)), sub_64))>;
25212525

2526+
def : Pat<(v4f32 (loongarch_vfcvt_s_d (v2f64 LSX128:$vj), (v2f64 LSX128:$vk))),
2527+
(VFCVT_S_D LSX128:$vj, LSX128:$vk)>;
2528+
25222529
// load
25232530
def : Pat<(int_loongarch_lsx_vld GPR:$rj, timm:$imm),
25242531
(VLD GPR:$rj, (to_valid_timm timm:$imm))>;

‎llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptrunc.ll‎

Lines changed: 10 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -7,18 +7,9 @@ define void @fptrunc_v4f64_to_v4f32(ptr %res, ptr %a0) nounwind {
77
; CHECK-LABEL: fptrunc_v4f64_to_v4f32:
88
; CHECK: # %bb.0: # %entry
99
; CHECK-NEXT: xvld $xr0, $a1, 0
10-
; CHECK-NEXT: xvpickve.d $xr1, $xr0, 1
11-
; CHECK-NEXT: fcvt.s.d $fa1, $fa1
12-
; CHECK-NEXT: xvpickve.d $xr2, $xr0, 0
13-
; CHECK-NEXT: fcvt.s.d $fa2, $fa2
14-
; CHECK-NEXT: vextrins.w $vr2, $vr1, 16
15-
; CHECK-NEXT: xvpickve.d $xr1, $xr0, 2
16-
; CHECK-NEXT: fcvt.s.d $fa1, $fa1
17-
; CHECK-NEXT: vextrins.w $vr2, $vr1, 32
18-
; CHECK-NEXT: xvpickve.d $xr0, $xr0, 3
19-
; CHECK-NEXT: fcvt.s.d $fa0, $fa0
20-
; CHECK-NEXT: vextrins.w $vr2, $vr0, 48
21-
; CHECK-NEXT: vst $vr2, $a0, 0
10+
; CHECK-NEXT: xvpermi.q $xr1, $xr0, 1
11+
; CHECK-NEXT: vfcvt.s.d $vr0, $vr1, $vr0
12+
; CHECK-NEXT: vst $vr0, $a0, 0
2213
; CHECK-NEXT: ret
2314
entry:
2415
%v0 = load <4 x double>, ptr %a0
@@ -30,32 +21,13 @@ entry:
3021
define void @fptrunc_v8f64_to_v8f32(ptr %res, ptr %a0) nounwind {
3122
; CHECK-LABEL: fptrunc_v8f64_to_v8f32:
3223
; CHECK: # %bb.0: # %entry
33-
; CHECK-NEXT: xvld $xr0, $a1, 32
34-
; CHECK-NEXT: xvld $xr1, $a1, 0
35-
; CHECK-NEXT: xvpickve.d $xr2, $xr0, 1
36-
; CHECK-NEXT: fcvt.s.d $fa2, $fa2
37-
; CHECK-NEXT: xvpickve.d $xr3, $xr0, 0
38-
; CHECK-NEXT: fcvt.s.d $fa3, $fa3
39-
; CHECK-NEXT: vextrins.w $vr3, $vr2, 16
40-
; CHECK-NEXT: xvpickve.d $xr2, $xr0, 2
41-
; CHECK-NEXT: fcvt.s.d $fa2, $fa2
42-
; CHECK-NEXT: vextrins.w $vr3, $vr2, 32
43-
; CHECK-NEXT: xvpickve.d $xr0, $xr0, 3
44-
; CHECK-NEXT: fcvt.s.d $fa0, $fa0
45-
; CHECK-NEXT: vextrins.w $vr3, $vr0, 48
46-
; CHECK-NEXT: xvpickve.d $xr0, $xr1, 1
47-
; CHECK-NEXT: fcvt.s.d $fa0, $fa0
48-
; CHECK-NEXT: xvpickve.d $xr2, $xr1, 0
49-
; CHECK-NEXT: fcvt.s.d $fa2, $fa2
50-
; CHECK-NEXT: vextrins.w $vr2, $vr0, 16
51-
; CHECK-NEXT: xvpickve.d $xr0, $xr1, 2
52-
; CHECK-NEXT: fcvt.s.d $fa0, $fa0
53-
; CHECK-NEXT: vextrins.w $vr2, $vr0, 32
54-
; CHECK-NEXT: xvpickve.d $xr0, $xr1, 3
55-
; CHECK-NEXT: fcvt.s.d $fa0, $fa0
56-
; CHECK-NEXT: vextrins.w $vr2, $vr0, 48
57-
; CHECK-NEXT: xvpermi.q $xr2, $xr3, 2
58-
; CHECK-NEXT: xvst $xr2, $a0, 0
24+
; CHECK-NEXT: xvld $xr0, $a1, 0
25+
; CHECK-NEXT: xvld $xr1, $a1, 32
26+
; CHECK-NEXT: pcalau12i $a1, %pc_hi20(.LCPI1_0)
27+
; CHECK-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI1_0)
28+
; CHECK-NEXT: xvfcvt.s.d $xr0, $xr1, $xr0
29+
; CHECK-NEXT: xvperm.w $xr0, $xr0, $xr2
30+
; CHECK-NEXT: xvst $xr0, $a0, 0
5931
; CHECK-NEXT: ret
6032
entry:
6133
%v0 = load <8 x double>, ptr %a0

‎llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptrunc.ll‎

Lines changed: 5 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -21,22 +21,15 @@ define void @fptrunc_v2f64_to_v2f32(ptr %res, ptr %a0) nounwind {
2121
; LA32-LABEL: fptrunc_v2f64_to_v2f32:
2222
; LA32: # %bb.0: # %entry
2323
; LA32-NEXT: vld $vr0, $a1, 0
24-
; LA32-NEXT: vreplvei.d $vr1, $vr0, 0
25-
; LA32-NEXT: fcvt.s.d $fa1, $fa1
26-
; LA32-NEXT: vreplvei.d $vr0, $vr0, 1
27-
; LA32-NEXT: fcvt.s.d $fa0, $fa0
28-
; LA32-NEXT: fst.s $fa0, $a0, 4
29-
; LA32-NEXT: fst.s $fa1, $a0, 0
24+
; LA32-NEXT: vfcvt.s.d $vr0, $vr0, $vr0
25+
; LA32-NEXT: vstelm.w $vr0, $a0, 4, 1
26+
; LA32-NEXT: vstelm.w $vr0, $a0, 0, 0
3027
; LA32-NEXT: ret
3128
;
3229
; LA64-LABEL: fptrunc_v2f64_to_v2f32:
3330
; LA64: # %bb.0: # %entry
3431
; LA64-NEXT: vld $vr0, $a1, 0
35-
; LA64-NEXT: vreplvei.d $vr1, $vr0, 1
36-
; LA64-NEXT: fcvt.s.d $fa1, $fa1
37-
; LA64-NEXT: vreplvei.d $vr0, $vr0, 0
38-
; LA64-NEXT: fcvt.s.d $fa0, $fa0
39-
; LA64-NEXT: vextrins.w $vr0, $vr1, 16
32+
; LA64-NEXT: vfcvt.s.d $vr0, $vr0, $vr0
4033
; LA64-NEXT: vstelm.d $vr0, $a0, 0, 0
4134
; LA64-NEXT: ret
4235
entry:
@@ -51,17 +44,7 @@ define void @fptrunc_v4f64_to_v4f32(ptr %res, ptr %a0) nounwind {
5144
; CHECK: # %bb.0: # %entry
5245
; CHECK-NEXT: vld $vr0, $a1, 0
5346
; CHECK-NEXT: vld $vr1, $a1, 16
54-
; CHECK-NEXT: vreplvei.d $vr2, $vr0, 1
55-
; CHECK-NEXT: fcvt.s.d $fa2, $fa2
56-
; CHECK-NEXT: vreplvei.d $vr0, $vr0, 0
57-
; CHECK-NEXT: fcvt.s.d $fa0, $fa0
58-
; CHECK-NEXT: vextrins.w $vr0, $vr2, 16
59-
; CHECK-NEXT: vreplvei.d $vr2, $vr1, 0
60-
; CHECK-NEXT: fcvt.s.d $fa2, $fa2
61-
; CHECK-NEXT: vextrins.w $vr0, $vr2, 32
62-
; CHECK-NEXT: vreplvei.d $vr1, $vr1, 1
63-
; CHECK-NEXT: fcvt.s.d $fa1, $fa1
64-
; CHECK-NEXT: vextrins.w $vr0, $vr1, 48
47+
; CHECK-NEXT: vfcvt.s.d $vr0, $vr1, $vr0
6548
; CHECK-NEXT: vst $vr0, $a0, 0
6649
; CHECK-NEXT: ret
6750
entry:

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