@@ -2769,12 +2769,15 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
27692769 // available.
27702770 if (!TmpReg)
27712771 TmpReg = RS->scavengeRegisterBackwards (AMDGPU::SReg_32_XM0RegClass,
2772- MI, false , 0 );
2773- BuildMI (*MBB, *MI, DL, TII->get (AMDGPU::S_LSHR_B32))
2774- .addDef (TmpReg, RegState::Renamable)
2775- .addReg (FrameReg)
2776- .addImm (ST.getWavefrontSizeLog2 ())
2777- .setOperandDead (3 ); // Set SCC dead
2772+ MI, /* RestoreAfter=*/ false , 0 ,
2773+ /* AllowSpill=*/ false );
2774+ if (TmpReg) {
2775+ BuildMI (*MBB, *MI, DL, TII->get (AMDGPU::S_LSHR_B32))
2776+ .addDef (TmpReg, RegState::Renamable)
2777+ .addReg (FrameReg)
2778+ .addImm (ST.getWavefrontSizeLog2 ())
2779+ .setOperandDead (3 ); // Set SCC dead
2780+ }
27782781 MaterializedReg = TmpReg;
27792782 }
27802783
@@ -2802,18 +2805,20 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
28022805 DstReg = TmpReg;
28032806 }
28042807
2805- auto AddI32 = BuildMI (*MBB, *MI, DL, MI->getDesc ())
2806- .addDef (DstReg, RegState::Renamable)
2807- .addReg (MaterializedReg, RegState::Kill)
2808- .add (OtherOp);
2809- if (DeadSCC)
2810- AddI32.setOperandDead (3 );
2808+ if (TmpReg) {
2809+ auto AddI32 = BuildMI (*MBB, *MI, DL, MI->getDesc ())
2810+ .addDef (DstReg, RegState::Renamable)
2811+ .addReg (MaterializedReg, RegState::Kill)
2812+ .add (OtherOp);
2813+ if (DeadSCC)
2814+ AddI32.setOperandDead (3 );
28112815
2812- MaterializedReg = DstReg;
2816+ MaterializedReg = DstReg;
28132817
2814- OtherOp.ChangeToRegister (MaterializedReg, false );
2815- OtherOp.setIsKill (true );
2816- OtherOp.setIsRenamable (true );
2818+ OtherOp.ChangeToRegister (MaterializedReg, false );
2819+ OtherOp.setIsKill (true );
2820+ OtherOp.setIsRenamable (true );
2821+ }
28172822 FIOp->ChangeToImmediate (Offset);
28182823 } else {
28192824 // If we don't have any other offset to apply, we can just directly
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