Address review comments

Author: phoebewang

llvm/lib/Target/X86/X86InstrInfo.cpp

@@ -5352,12 +5352,12 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
   MachineInstr *MI = nullptr;
   MachineInstr *Sub = nullptr;
   MachineInstr *Movr0Inst = nullptr;
-  SmallVector<MachineInstr *, 4> NDDInsts;
+  SmallVector<std::pair<MachineInstr *, unsigned>, 4> InstsToUpdate;
   bool NoSignFlag = false;
   bool ClearsOverflowFlag = false;
   bool ShouldUpdateCC = false;
   bool IsSwapped = false;
-  bool HasCF = Subtarget.hasNF();
+  bool HasNF = Subtarget.hasNF();
   unsigned OpNo = 0;
   X86::CondCode NewCC = X86::COND_INVALID;
   int64_t ImmDelta = 0;
@@ -5443,10 +5443,13 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
           continue;
         }
 
-        // Try to replace NDD with NF instructions.
-        if (HasCF && X86II::hasNewDataDest(Inst.getDesc().TSFlags) &&
-            Inst.registerDefIsDead(X86::EFLAGS, TRI)) {
-          NDDInsts.push_back(&Inst);
+        // Try to replace non-NF with NF instructions.
+        if (HasNF && Inst.registerDefIsDead(X86::EFLAGS, TRI)) {
+          unsigned NewOp = X86::getNFVariant(Inst.getOpcode());
+          if (!NewOp)
+            return false;
+
+          InstsToUpdate.push_back(std::make_pair(&Inst, NewOp));
           continue;
         }
 
@@ -5646,10 +5649,10 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
       return false;
   }
 
-  // Replace NDD with NF instructions.
-  for (MachineInstr *NDD : NDDInsts) {
-    NDD->setDesc(get(X86::getNFVariant(NDD->getOpcode())));
-    NDD->removeOperand(NDD->getNumOperands() - 1);
+  // Replace non-NF with NF instructions.
+  for (auto &Inst : InstsToUpdate) {
+    Inst.first->setDesc(get(Inst.second));
+    Inst.first->removeOperand(Inst.first->getNumOperands() - 1);
   }
 
   // Make sure Sub instruction defines EFLAGS and mark the def live.

llvm/test/CodeGen/X86/apx/cf.ll

@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64 -mattr=+cf,+nf,+ndd,+avx512f -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64 -mattr=+cf,+nf,+avx512f -verify-machineinstrs | FileCheck %s
 
 define void @basic(i32 %a, ptr %b, ptr %p, ptr %q) {
 ; CHECK-LABEL: basic:
@@ -57,8 +57,9 @@ entry:
 define i64 @reduced_data_dependency(i64 %a, i64 %b, ptr %c) {
 ; CHECK-LABEL: reduced_data_dependency:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    subq %rsi, %rdi, %rax
-; CHECK-NEXT:    cfcmovnsq (%rdx), %rdi, %rcx
+; CHECK-NEXT:    movq %rdi, %rcx
+; CHECK-NEXT:    subq %rsi, %rcx
+; CHECK-NEXT:    cfcmovnsq (%rdx), %rdi, %rax
 ; CHECK-NEXT:    addq %rcx, %rax
 ; CHECK-NEXT:    retq
 entry:
@@ -144,7 +145,7 @@ define void @load_add_store(i32 %a, i32 %b, ptr %p) {
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpl %esi, %edi
 ; CHECK-NEXT:    cfcmovnew (%rdx), %ax
-; CHECK-NEXT:    {nf} incw %ax
+; CHECK-NEXT:    {nf} incl %eax
 ; CHECK-NEXT:    cfcmovnew %ax, (%rdx)
 ; CHECK-NEXT:    retq
 entry: