Change predicate match to expect same sign state

Author: bobby-b-song

llvm/lib/Analysis/InstructionSimplify.cpp

@@ -2182,12 +2182,14 @@ static Value *simplifyAndInst(Value *Op0, Value *Op1, const SimplifyQuery &Q,
             m_c_ICmp(Pred0, m_Value(X), m_Not(m_Value(Y)))) &&
       match(Op1, m_c_ICmp(Pred1, m_Specific(Y),
                           m_Not(m_Specific(X))))) {
-    if (ICmpInst::isLE(Pred0) && ICmpInst::isGT(Pred1))
-      return ConstantInt::getFalse(Op0->getType());
-    if (ICmpInst::isLT(Pred0) && ICmpInst::isGE(Pred1))
-      return ConstantInt::getFalse(Op0->getType());
-    if (ICmpInst::isLT(Pred0) && ICmpInst::isGT(Pred1))
-      return ConstantInt::getFalse(Op0->getType());
+    if (ICmpInst::isSigned(Pred0) == ICmpInst::isSigned(Pred1)) {
+      if (ICmpInst::isLE(Pred0) && ICmpInst::isGT(Pred1))
+        return ConstantInt::getFalse(Op0->getType());
+      if (ICmpInst::isLT(Pred0) && ICmpInst::isGE(Pred1))
+        return ConstantInt::getFalse(Op0->getType());
+      if (ICmpInst::isLT(Pred0) && ICmpInst::isGT(Pred1))
+        return ConstantInt::getFalse(Op0->getType());
+    }
   }
 
   if (Op0->getType()->isIntOrIntVectorTy(1)) {

llvm/test/Transforms/InstCombine/and-comparison-not-always-false.ll

@@ -136,3 +136,23 @@ common.ret:
   %common.ret.op = and i1 %6, %4
   ret i1 %common.ret.op
 }
+
+define i1 @test_no_change_su(i32 %0, i32 %1) {
+; CHECK-LABEL: define i1 @test_no_change_su(
+; CHECK-SAME: i32 [[TMP0:%.*]], i32 [[TMP1:%.*]]) {
+; CHECK-NEXT:  [[COMMON_RET:.*:]]
+; CHECK-NEXT:    [[TMP2:%.*]] = xor i32 [[TMP0]], -1
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = xor i32 [[TMP1]], -1
+; CHECK-NEXT:    [[TMP5:%.*]] = icmp ugt i32 [[TMP0]], [[TMP4]]
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = and i1 [[TMP3]], [[TMP5]]
+; CHECK-NEXT:    ret i1 [[COMMON_RET_OP]]
+;
+common.ret:
+  %2 = xor i32 %0, -1
+  %3 = icmp sle i32 %1, %2
+  %4 = xor i32 %1, -1
+  %5 = icmp ugt i32 %0, %4
+  %common.ret.op = and i1 %3, %5
+  ret i1 %common.ret.op
+}