Skip to content

Commit 1c8b6a0

Browse files
GeneraluseAIGeneraluseAI
committed
[CIR][X86] Implement lowering for pmuldq / pmuludq builtins
This patch adds CIR codegen support for X86 pmuldq and pmuludq operations, covering the signed and unsigned variants across all supported vector widths. The builtins now lower to the expected CIR representation matching the semantics of the corresponding LLVM intrinsics.
1 parent d20d84f commit 1c8b6a0

File tree

5 files changed

+239
-2
lines changed

5 files changed

+239
-2
lines changed

‎clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp‎

Lines changed: 50 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -130,6 +130,40 @@ static mlir::Value emitVecInsert(CIRGenBuilderTy &builder, mlir::Location loc,
130130
return cir::VecInsertOp::create(builder, loc, vec, value, indexVal);
131131
}
132132

133+
static mlir::Value emitX86Muldq(CIRGenBuilderTy &builder, mlir::Location loc,
134+
bool isSigned,
135+
SmallVectorImpl<mlir::Value> &ops,
136+
unsigned opTypePrimitiveSizeInBits) {
137+
mlir::Type ty = cir::VectorType::get(builder.getSInt64Ty(),
138+
opTypePrimitiveSizeInBits / 64);
139+
mlir::Value lhs = builder.createBitcast(loc, ops[0], ty);
140+
mlir::Value rhs = builder.createBitcast(loc, ops[1], ty);
141+
if (isSigned) {
142+
cir::ConstantOp shiftAmt =
143+
builder.getConstant(loc, cir::IntAttr::get(builder.getSInt64Ty(), 32));
144+
cir::VecSplatOp shiftSplatVecOp =
145+
cir::VecSplatOp::create(builder, loc, ty, shiftAmt.getResult());
146+
mlir::Value shiftSplatValue = shiftSplatVecOp.getResult();
147+
// In CIR, right-shift operations are automatically lowered to either an
148+
// arithmetic or logical shift depending on the operand type. The purpose
149+
// of the shifts here is to propagate the sign bit of the 32-bit input
150+
// into the upper bits of each vector lane.
151+
lhs = builder.createShift(loc, lhs, shiftSplatValue, true);
152+
lhs = builder.createShift(loc, lhs, shiftSplatValue, false);
153+
rhs = builder.createShift(loc, rhs, shiftSplatValue, true);
154+
rhs = builder.createShift(loc, rhs, shiftSplatValue, false);
155+
} else {
156+
cir::ConstantOp maskScalar = builder.getConstant(
157+
loc, cir::IntAttr::get(builder.getSInt64Ty(), 0xffffffff));
158+
cir::VecSplatOp mask =
159+
cir::VecSplatOp::create(builder, loc, ty, maskScalar.getResult());
160+
// Clear the upper bits
161+
lhs = builder.createAnd(loc, lhs, mask);
162+
rhs = builder.createAnd(loc, rhs, mask);
163+
}
164+
return builder.createMul(loc, lhs, rhs);
165+
}
166+
133167
mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID,
134168
const CallExpr *expr) {
135169
if (builtinID == Builtin::BI__builtin_cpu_is) {
@@ -956,12 +990,26 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID,
956990
case X86::BI__builtin_ia32_sqrtph512:
957991
case X86::BI__builtin_ia32_sqrtps512:
958992
case X86::BI__builtin_ia32_sqrtpd512:
993+
cgm.errorNYI(expr->getSourceRange(),
994+
std::string("unimplemented X86 builtin call: ") +
995+
getContext().BuiltinInfo.getName(builtinID));
996+
return {};
959997
case X86::BI__builtin_ia32_pmuludq128:
960998
case X86::BI__builtin_ia32_pmuludq256:
961-
case X86::BI__builtin_ia32_pmuludq512:
999+
case X86::BI__builtin_ia32_pmuludq512: {
1000+
unsigned opTypePrimitiveSizeInBits =
1001+
cgm.getDataLayout().getTypeSizeInBits(ops[0].getType());
1002+
return emitX86Muldq(builder, getLoc(expr->getExprLoc()), /*isSigned*/ false,
1003+
ops, opTypePrimitiveSizeInBits);
1004+
}
9621005
case X86::BI__builtin_ia32_pmuldq128:
9631006
case X86::BI__builtin_ia32_pmuldq256:
964-
case X86::BI__builtin_ia32_pmuldq512:
1007+
case X86::BI__builtin_ia32_pmuldq512: {
1008+
unsigned opTypePrimitiveSizeInBits =
1009+
cgm.getDataLayout().getTypeSizeInBits(ops[0].getType());
1010+
return emitX86Muldq(builder, getLoc(expr->getExprLoc()), /*isSigned*/ true,
1011+
ops, opTypePrimitiveSizeInBits);
1012+
}
9651013
case X86::BI__builtin_ia32_pternlogd512_mask:
9661014
case X86::BI__builtin_ia32_pternlogq512_mask:
9671015
case X86::BI__builtin_ia32_pternlogd128_mask:

‎clang/test/CIR/CodeGenBuiltins/X86/avx2-builtins.c‎

Lines changed: 68 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,68 @@
1+
// RUN: %clang_cc1 -x c -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-linux -target-feature +avx2 -fclangir -emit-cir -o %t.cir -Wall -Werror -Wsign-conversion
2+
// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
3+
// RUN: %clang_cc1 -x c -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-linux -target-feature +avx2 -fclangir -emit-llvm -o %t.ll -Wall -Werror -Wsign-conversion
4+
// RUN: FileCheck --check-prefixes=LLVM --input-file=%t.ll %s
5+
6+
// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-linux -target-feature +avx2 -fclangir -emit-cir -o %t.cir -Wall -Werror -Wsign-conversion
7+
// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
8+
// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-linux -target-feature +avx2 -fclangir -emit-llvm -o %t.ll -Wall -Werror -Wsign-conversion
9+
// RUN: FileCheck --check-prefixes=LLVM --input-file=%t.ll %s
10+
11+
// RUN: %clang_cc1 -x c -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx2 -emit-llvm -o - -Wall -Werror -Wsign-conversion | FileCheck %s --check-prefixes=OGCG
12+
// RUN: %clang_cc1 -x c -flax-vector-conversions=none -fms-extensions -fms-compatibility -ffreestanding %s -triple=x86_64-windows-msvc -target-feature +avx2 -emit-llvm -o - -Wall -Werror -Wsign-conversion | FileCheck %s --check-prefixes=OGCG
13+
// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx2 -emit-llvm -o - -Wall -Werror -Wsign-conversion | FileCheck %s --check-prefixes=OGCG
14+
// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -fms-extensions -fms-compatibility -ffreestanding %s -triple=x86_64-windows-msvc -target-feature +avx2 -emit-llvm -o - -Wall -Werror -Wsign-conversion | FileCheck %s --check-prefixes=OGCG
15+
16+
#include <immintrin.h>
17+
18+
__m256i test_mm256_mul_epu32(__m256i a, __m256i b) {
19+
// CIR-LABEL: _mm256_mul_epu32
20+
// CIR: [[BC_A:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !s64i>
21+
// CIR: [[BC_B:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !s64i>
22+
// CIR: [[MASK_SCALAR:%.*]] = cir.const #cir.int<4294967295> : !s64i
23+
// CIR: [[MASK_VEC:%.*]] = cir.vec.splat [[MASK_SCALAR]] : !s64i, !cir.vector<4 x !s64i>
24+
// CIR: [[AND_A:%.*]] = cir.binop(and, [[BC_A]], [[MASK_VEC]])
25+
// CIR: [[AND_B:%.*]] = cir.binop(and, [[BC_B]], [[MASK_VEC]])
26+
// CIR: [[MUL:%.*]] = cir.binop(mul, [[AND_A]], [[AND_B]])
27+
28+
// LLVM-LABEL: _mm256_mul_epu32
29+
// LLVM: and <4 x i64> %{{.*}}, splat (i64 4294967295)
30+
// LLVM: and <4 x i64> %{{.*}}, splat (i64 4294967295)
31+
// LLVM: mul <4 x i64> %{{.*}}, %{{.*}}
32+
33+
// OGCG-LABEL: _mm256_mul_epu32
34+
// OGCG: and <4 x i64> %{{.*}}, splat (i64 4294967295)
35+
// OGCG: and <4 x i64> %{{.*}}, splat (i64 4294967295)
36+
// OGCG: mul <4 x i64> %{{.*}}, %{{.*}}
37+
38+
return _mm256_mul_epu32(a, b);
39+
}
40+
41+
__m256i test_mm256_mul_epi32(__m256i a, __m256i b) {
42+
// CIR-LABEL: _mm256_mul_epi32
43+
// CIR: [[A64:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !s64i>
44+
// CIR: [[B64:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<4 x !s64i>
45+
// CIR: [[SC:%.*]] = cir.const #cir.int<32> : !s64i
46+
// CIR: [[SV:%.*]] = cir.vec.splat [[SC]] : !s64i, !cir.vector<4 x !s64i>
47+
// CIR: [[SHL_A:%.*]] = cir.shift(left, [[A64]] : !cir.vector<4 x !s64i>, [[SV]] : !cir.vector<4 x !s64i>)
48+
// CIR: [[ASHR_A:%.*]] = cir.shift(right, [[SHL_A]] : !cir.vector<4 x !s64i>, [[SV]] : !cir.vector<4 x !s64i>)
49+
// CIR: [[SHL_B:%.*]] = cir.shift(left, [[B64]] : !cir.vector<4 x !s64i>, [[SV]] : !cir.vector<4 x !s64i>)
50+
// CIR: [[ASHR_B:%.*]] = cir.shift(right, [[SHL_B]] : !cir.vector<4 x !s64i>, [[SV]] : !cir.vector<4 x !s64i>)
51+
// CIR: [[MUL:%.*]] = cir.binop(mul, [[ASHR_A]], [[ASHR_B]])
52+
53+
// LLVM-LABEL: _mm256_mul_epi32
54+
// LLVM: shl <4 x i64> %{{.*}}, splat (i64 32)
55+
// LLVM: ashr <4 x i64> %{{.*}}, splat (i64 32)
56+
// LLVM: shl <4 x i64> %{{.*}}, splat (i64 32)
57+
// LLVM: ashr <4 x i64> %{{.*}}, splat (i64 32)
58+
// LLVM: mul <4 x i64> %{{.*}}, %{{.*}}
59+
60+
// OGCG-LABEL: _mm256_mul_epi32
61+
// OGCG: shl <4 x i64> %{{.*}}, splat (i64 32)
62+
// OGCG: ashr <4 x i64> %{{.*}}, splat (i64 32)
63+
// OGCG: shl <4 x i64> %{{.*}}, splat (i64 32)
64+
// OGCG: ashr <4 x i64> %{{.*}}, splat (i64 32)
65+
// OGCG: mul <4 x i64> %{{.*}}, %{{.*}}
66+
67+
return _mm256_mul_epi32(a, b);
68+
}

‎clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c‎

100644100755
Lines changed: 53 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -419,3 +419,56 @@ __m512i test_mm512_mask_i32gather_epi64(__m512i __v1_old, __mmask8 __mask, __m25
419419
// OGCG: call <8 x i64> @llvm.x86.avx512.mask.gather.dpq.512
420420
return _mm512_mask_i32gather_epi64(__v1_old, __mask, __index, __addr, 2);
421421
}
422+
423+
__m512i test_mm512_mul_epi32(__m512i __A, __m512i __B) {
424+
// CIR-LABEL: _mm512_mul_epi32
425+
// CIR: [[A64:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<16 x !s32i> -> !cir.vector<8 x !s64i>
426+
// CIR: [[B64:%.*]] = cir.cast bitcast %{{.*}} : !cir.vector<16 x !s32i> -> !cir.vector<8 x !s64i>
427+
// CIR: [[SC:%.*]] = cir.const #cir.int<32> : !s64i
428+
// CIR: [[SV:%.*]] = cir.vec.splat [[SC]] : !s64i, !cir.vector<8 x !s64i>
429+
// CIR: [[SHL_A:%.*]] = cir.shift(left, [[A64]] : !cir.vector<8 x !s64i>, [[SV]] : !cir.vector<8 x !s64i>)
430+
// CIR: [[ASHR_A:%.*]] = cir.shift(right, [[SHL_A]] : !cir.vector<8 x !s64i>, [[SV]] : !cir.vector<8 x !s64i>)
431+
// CIR: [[SHL_B:%.*]] = cir.shift(left, [[B64]] : !cir.vector<8 x !s64i>, [[SV]] : !cir.vector<8 x !s64i>)
432+
// CIR: [[ASHR_B:%.*]] = cir.shift(right, [[SHL_B]] : !cir.vector<8 x !s64i>, [[SV]] : !cir.vector<8 x !s64i>)
433+
// CIR: [[MUL:%.*]] = cir.binop(mul, [[ASHR_A]], [[ASHR_B]])
434+
435+
// LLVM-LABEL: _mm512_mul_epi32
436+
// LLVM: shl <8 x i64> %{{.*}}, splat (i64 32)
437+
// LLVM: ashr <8 x i64> %{{.*}}, splat (i64 32)
438+
// LLVM: shl <8 x i64> %{{.*}}, splat (i64 32)
439+
// LLVM: ashr <8 x i64> %{{.*}}, splat (i64 32)
440+
// LLVM: mul <8 x i64> %{{.*}}, %{{.*}}
441+
442+
// OGCG-LABEL: _mm512_mul_epi32
443+
// OGCG: shl <8 x i64> %{{.*}}, splat (i64 32)
444+
// OGCG: ashr <8 x i64> %{{.*}}, splat (i64 32)
445+
// OGCG: shl <8 x i64> %{{.*}}, splat (i64 32)
446+
// OGCG: ashr <8 x i64> %{{.*}}, splat (i64 32)
447+
// OGCG: mul <8 x i64> %{{.*}}, %{{.*}}
448+
449+
return _mm512_mul_epi32(__A, __B);
450+
}
451+
452+
453+
__m512i test_mm512_mul_epu32(__m512i __A, __m512i __B) {
454+
// CIR-LABEL: _mm512_mul_epu32
455+
// CIR: [[BC_A:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<8 x !s64i>
456+
// CIR: [[BC_B:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<8 x !s64i>
457+
// CIR: [[MASK_SCALAR:%.*]] = cir.const #cir.int<4294967295> : !s64i
458+
// CIR: [[MASK_VEC:%.*]] = cir.vec.splat [[MASK_SCALAR]] : !s64i, !cir.vector<8 x !s64i>
459+
// CIR: [[AND_A:%.*]] = cir.binop(and, [[BC_A]], [[MASK_VEC]])
460+
// CIR: [[AND_B:%.*]] = cir.binop(and, [[BC_B]], [[MASK_VEC]])
461+
// CIR: [[MUL:%.*]] = cir.binop(mul, [[AND_A]], [[AND_B]])
462+
463+
// LLVM-LABEL: _mm512_mul_epu32
464+
// LLVM: and <8 x i64> %{{.*}}, splat (i64 4294967295)
465+
// LLVM: and <8 x i64> %{{.*}}, splat (i64 4294967295)
466+
// LLVM: mul <8 x i64> %{{.*}}, %{{.*}}
467+
468+
// OGCG-LABEL: _mm512_mul_epu32
469+
// OGCG: and <8 x i64> %{{.*}}, splat (i64 4294967295)
470+
// OGCG: and <8 x i64> %{{.*}}, splat (i64 4294967295)
471+
// OGCG: mul <8 x i64> %{{.*}}, %{{.*}}
472+
473+
return _mm512_mul_epu32(__A, __B);
474+
}

‎clang/test/CIR/CodeGenBuiltins/X86/sse2-builtins.c‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -108,3 +108,26 @@ void test_mm_pause(void) {
108108
// LLVM: call void @llvm.x86.sse2.pause()
109109
// OGCG: call void @llvm.x86.sse2.pause()
110110
}
111+
112+
__m128i test_mm_mul_epu32(__m128i A, __m128i B) {
113+
// CIR-LABEL: _mm_mul_epu32
114+
// CIR: [[BC_A:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !s64i>
115+
// CIR: [[BC_B:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !s64i>
116+
// CIR: [[MASK_SCALAR:%.*]] = cir.const #cir.int<4294967295> : !s64i
117+
// CIR: [[MASK_VEC:%.*]] = cir.vec.splat [[MASK_SCALAR]] : !s64i, !cir.vector<2 x !s64i>
118+
// CIR: [[AND_A:%.*]] = cir.binop(and, [[BC_A]], [[MASK_VEC]])
119+
// CIR: [[AND_B:%.*]] = cir.binop(and, [[BC_B]], [[MASK_VEC]])
120+
// CIR: [[MUL:%.*]] = cir.binop(mul, [[AND_A]], [[AND_B]])
121+
122+
// LLVM-LABEL: _mm_mul_epu32
123+
// LLVM: and <2 x i64> %{{.*}}, splat (i64 4294967295)
124+
// LLVM: and <2 x i64> %{{.*}}, splat (i64 4294967295)
125+
// LLVM: mul <2 x i64> %{{.*}}, %{{.*}}
126+
127+
// OGCG-LABEL: _mm_mul_epu32
128+
// OGCG: and <2 x i64> %{{.*}}, splat (i64 4294967295)
129+
// OGCG: and <2 x i64> %{{.*}}, splat (i64 4294967295)
130+
// OGCG: mul <2 x i64> %{{.*}}, %{{.*}}
131+
132+
return _mm_mul_epu32(A, B);
133+
}

‎clang/test/CIR/CodeGenBuiltins/X86/sse41-builtins.c‎

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,45 @@
1+
// RUN: %clang_cc1 -x c -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-linux -target-feature +sse4.1 -fclangir -emit-cir -o %t.cir -Wall -Werror -Wsign-conversion
2+
// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
3+
// RUN: %clang_cc1 -x c -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-linux -target-feature +sse4.1 -fclangir -emit-llvm -o %t.ll -Wall -Werror -Wsign-conversion
4+
// RUN: FileCheck --check-prefixes=LLVM --input-file=%t.ll %s
5+
6+
// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-linux -target-feature +sse4.1 -fclangir -emit-cir -o %t.cir -Wall -Werror -Wsign-conversion
7+
// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
8+
// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-linux -target-feature +sse4.1 -fclangir -emit-llvm -o %t.ll -Wall -Werror -Wsign-conversion
9+
// RUN: FileCheck --check-prefixes=LLVM --input-file=%t.ll %s
10+
11+
// RUN: %clang_cc1 -x c -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +sse4.1 -emit-llvm -o - -Wall -Werror -Wsign-conversion | FileCheck %s --check-prefixes=OGCG
12+
// RUN: %clang_cc1 -x c -flax-vector-conversions=none -fms-extensions -fms-compatibility -ffreestanding %s -triple=x86_64-windows-msvc -target-feature +sse4.1 -emit-llvm -o - -Wall -Werror -Wsign-conversion | FileCheck %s --check-prefixes=OGCG
13+
// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +sse4.1 -emit-llvm -o - -Wall -Werror -Wsign-conversion | FileCheck %s --check-prefixes=OGCG
14+
// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -fms-extensions -fms-compatibility -ffreestanding %s -triple=x86_64-windows-msvc -target-feature +sse4.1 -emit-llvm -o - -Wall -Werror -Wsign-conversion | FileCheck %s --check-prefixes=OGCG
15+
16+
#include <immintrin.h>
17+
18+
__m128i test_mm_mul_epi32(__m128i x, __m128i y) {
19+
// CIR-LABEL: _mm_mul_epi32
20+
// CIR: [[A64:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !s64i>
21+
// CIR: [[B64:%.*]] = cir.cast bitcast %{{.*}} : {{.*}} -> !cir.vector<2 x !s64i>
22+
// CIR: [[SC:%.*]] = cir.const #cir.int<32> : !s64i
23+
// CIR: [[SV:%.*]] = cir.vec.splat [[SC]] : !s64i, !cir.vector<2 x !s64i>
24+
// CIR: [[SHL_A:%.*]] = cir.shift(left, [[A64]] : !cir.vector<2 x !s64i>, [[SV]] : !cir.vector<2 x !s64i>)
25+
// CIR: [[ASHR_A:%.*]] = cir.shift(right, [[SHL_A]] : !cir.vector<2 x !s64i>, [[SV]] : !cir.vector<2 x !s64i>)
26+
// CIR: [[SHL_B:%.*]] = cir.shift(left, [[B64]] : !cir.vector<2 x !s64i>, [[SV]] : !cir.vector<2 x !s64i>)
27+
// CIR: [[ASHR_B:%.*]] = cir.shift(right, [[SHL_B]] : !cir.vector<2 x !s64i>, [[SV]] : !cir.vector<2 x !s64i>)
28+
// CIR: [[MUL:%.*]] = cir.binop(mul, [[ASHR_A]], [[ASHR_B]])
29+
30+
// LLVM-LABEL: _mm_mul_epi32
31+
// LLVM: shl <2 x i64> %{{.*}}, splat (i64 32)
32+
// LLVM: ashr <2 x i64> %{{.*}}, splat (i64 32)
33+
// LLVM: shl <2 x i64> %{{.*}}, splat (i64 32)
34+
// LLVM: ashr <2 x i64> %{{.*}}, splat (i64 32)
35+
// LLVM: mul <2 x i64> %{{.*}}, %{{.*}}
36+
37+
// OGCG-LABEL: _mm_mul_epi32
38+
// OGCG: shl <2 x i64> %{{.*}}, splat (i64 32)
39+
// OGCG: ashr <2 x i64> %{{.*}}, splat (i64 32)
40+
// OGCG: shl <2 x i64> %{{.*}}, splat (i64 32)
41+
// OGCG: ashr <2 x i64> %{{.*}}, splat (i64 32)
42+
// OGCG: mul <2 x i64> %{{.*}}, %{{.*}}
43+
44+
return _mm_mul_epi32(x, y);
45+
}

0 commit comments

Comments
 (0)