Skip to content

Commit 1cbc7c5

Browse files
rampitecrampitec
committed
[AMDGPU] gfx1250 64-bit relocations and fixups
1 parent 66e707e commit 1cbc7c5

16 files changed

+287
-25
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5734,6 +5734,7 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
57345734
NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
57355735
NODE_NAME_CASE(CONST_DATA_PTR)
57365736
NODE_NAME_CASE(PC_ADD_REL_OFFSET)
5737+
NODE_NAME_CASE(PC_ADD_REL_OFFSET64)
57375738
NODE_NAME_CASE(LDS)
57385739
NODE_NAME_CASE(DUMMY_CHAIN)
57395740
NODE_NAME_CASE(LOAD_D16_HI)

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -545,6 +545,7 @@ enum NodeType : unsigned {
545545
/// Pointer to the start of the shader's constant data.
546546
CONST_DATA_PTR,
547547
PC_ADD_REL_OFFSET,
548+
PC_ADD_REL_OFFSET64,
548549
LDS,
549550

550551
DUMMY_CHAIN,

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp‎

Lines changed: 24 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2932,14 +2932,22 @@ bool AMDGPULegalizerInfo::buildPCRelGlobalAddress(Register DstReg, LLT PtrTy,
29322932
Register PCReg = PtrTy.getSizeInBits() != 32 ? DstReg :
29332933
B.getMRI()->createGenericVirtualRegister(ConstPtrTy);
29342934

2935-
MachineInstrBuilder MIB = B.buildInstr(AMDGPU::SI_PC_ADD_REL_OFFSET)
2936-
.addDef(PCReg);
2935+
if (ST.has64BitLiterals()) {
2936+
assert(GAFlags != SIInstrInfo::MO_NONE);
29372937

2938-
MIB.addGlobalAddress(GV, Offset, GAFlags);
2939-
if (GAFlags == SIInstrInfo::MO_NONE)
2940-
MIB.addImm(0);
2941-
else
2942-
MIB.addGlobalAddress(GV, Offset, GAFlags + 1);
2938+
MachineInstrBuilder MIB =
2939+
B.buildInstr(AMDGPU::SI_PC_ADD_REL_OFFSET64).addDef(PCReg);
2940+
MIB.addGlobalAddress(GV, Offset, GAFlags + 2);
2941+
} else {
2942+
MachineInstrBuilder MIB =
2943+
B.buildInstr(AMDGPU::SI_PC_ADD_REL_OFFSET).addDef(PCReg);
2944+
2945+
MIB.addGlobalAddress(GV, Offset, GAFlags);
2946+
if (GAFlags == SIInstrInfo::MO_NONE)
2947+
MIB.addImm(0);
2948+
else
2949+
MIB.addGlobalAddress(GV, Offset, GAFlags + 1);
2950+
}
29432951

29442952
if (!B.getMRI()->getRegClassOrNull(PCReg))
29452953
B.getMRI()->setRegClass(PCReg, &AMDGPU::SReg_64RegClass);
@@ -2955,6 +2963,15 @@ void AMDGPULegalizerInfo::buildAbsGlobalAddress(
29552963
MachineRegisterInfo &MRI) const {
29562964
bool RequiresHighHalf = PtrTy.getSizeInBits() != 32;
29572965

2966+
if (RequiresHighHalf && ST.has64BitLiterals()) {
2967+
if (!MRI.getRegClassOrNull(DstReg))
2968+
MRI.setRegClass(DstReg, &AMDGPU::SReg_64RegClass);
2969+
B.buildInstr(AMDGPU::S_MOV_B64)
2970+
.addDef(DstReg)
2971+
.addGlobalAddress(GV, 0, SIInstrInfo::MO_ABS64);
2972+
return;
2973+
}
2974+
29582975
LLT S32 = LLT::scalar(32);
29592976

29602977
// Use the destination directly, if and only if we store the lower address

‎llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,7 @@ static AMDGPUMCExpr::Specifier getSpecifier(unsigned MOFlags) {
5050
default:
5151
return AMDGPUMCExpr::S_None;
5252
case SIInstrInfo::MO_GOTPCREL:
53+
case SIInstrInfo::MO_GOTPCREL64:
5354
return AMDGPUMCExpr::S_GOTPCREL;
5455
case SIInstrInfo::MO_GOTPCREL32_LO:
5556
return AMDGPUMCExpr::S_GOTPCREL32_LO;
@@ -59,10 +60,14 @@ static AMDGPUMCExpr::Specifier getSpecifier(unsigned MOFlags) {
5960
return AMDGPUMCExpr::S_REL32_LO;
6061
case SIInstrInfo::MO_REL32_HI:
6162
return AMDGPUMCExpr::S_REL32_HI;
63+
case SIInstrInfo::MO_REL64:
64+
return AMDGPUMCExpr::S_REL64;
6265
case SIInstrInfo::MO_ABS32_LO:
6366
return AMDGPUMCExpr::S_ABS32_LO;
6467
case SIInstrInfo::MO_ABS32_HI:
6568
return AMDGPUMCExpr::S_ABS32_HI;
69+
case SIInstrInfo::MO_ABS64:
70+
return AMDGPUMCExpr::S_ABS64;
6671
}
6772
}
6873

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -64,6 +64,8 @@ unsigned AMDGPUELFObjectWriter::getRelocType(const MCFixup &Fixup,
6464
return ELF::R_AMDGPU_ABS32_LO;
6565
case AMDGPUMCExpr::S_ABS32_HI:
6666
return ELF::R_AMDGPU_ABS32_HI;
67+
case AMDGPUMCExpr::S_ABS64:
68+
return ELF::R_AMDGPU_ABS64;
6769
}
6870

6971
MCFixupKind Kind = Fixup.getKind();

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@ const MCAsmInfo::AtSpecifier atSpecifiers[] = {
2525
{AMDGPUMCExpr::S_REL64, "rel64"},
2626
{AMDGPUMCExpr::S_ABS32_LO, "abs32@lo"},
2727
{AMDGPUMCExpr::S_ABS32_HI, "abs32@hi"},
28+
{AMDGPUMCExpr::S_ABS64, "abs64"},
2829
};
2930

3031
AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT,

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp‎

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -564,7 +564,8 @@ static bool needsPCRel(const MCExpr *Expr) {
564564
case MCExpr::SymbolRef: {
565565
auto *SE = cast<MCSymbolRefExpr>(Expr);
566566
auto Spec = AMDGPU::getSpecifier(SE);
567-
return Spec != AMDGPUMCExpr::S_ABS32_LO && Spec != AMDGPUMCExpr::S_ABS32_HI;
567+
return Spec != AMDGPUMCExpr::S_ABS32_LO &&
568+
Spec != AMDGPUMCExpr::S_ABS32_HI && Spec != AMDGPUMCExpr::S_ABS64;
568569
}
569570
case MCExpr::Binary: {
570571
auto *BE = cast<MCBinaryExpr>(Expr);
@@ -687,7 +688,12 @@ void AMDGPUMCCodeEmitter::getMachineOpValueCommon(
687688
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
688689
uint32_t Offset = Desc.getSize();
689690
assert(Offset == 4 || Offset == 8);
690-
addFixup(Fixups, Offset, MO.getExpr(), FK_Data_4, PCRel);
691+
auto OpType = Desc.operands()[OpNo].OperandType;
692+
MCFixupKind Kind = (STI.hasFeature(AMDGPU::Feature64BitLiterals) &&
693+
OpType == AMDGPU::OPERAND_REG_IMM_INT64)
694+
? FK_Data_8
695+
: FK_Data_4;
696+
addFixup(Fixups, Offset, MO.getExpr(), Kind, PCRel);
691697
}
692698

693699
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,7 @@ class AMDGPUMCExpr : public MCTargetExpr {
5050
S_REL64, // symbol@rel64
5151
S_ABS32_LO, // symbol@abs32@lo
5252
S_ABS32_HI, // symbol@abs32@hi
53+
S_ABS64, // symbol@abs64
5354
};
5455

5556
private:

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8166,6 +8166,14 @@ buildPCRelGlobalAddress(SelectionDAG &DAG, const GlobalValue *GV,
81668166
// $symbol@*@hi with lower 32 bits and higher 32 bits of a literal constant,
81678167
// which is a 64-bit pc-relative offset from the encoding of the $symbol
81688168
// operand to the global variable.
8169+
if (((const GCNSubtarget &)DAG.getSubtarget()).has64BitLiterals()) {
8170+
assert(GAFlags != SIInstrInfo::MO_NONE);
8171+
8172+
SDValue Ptr =
8173+
DAG.getTargetGlobalAddress(GV, DL, MVT::i64, Offset, GAFlags + 2);
8174+
return DAG.getNode(AMDGPUISD::PC_ADD_REL_OFFSET64, DL, PtrVT, Ptr);
8175+
}
8176+
81698177
SDValue PtrLo = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset, GAFlags);
81708178
SDValue PtrHi;
81718179
if (GAFlags == SIInstrInfo::MO_NONE)
@@ -8215,6 +8223,13 @@ SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
82158223
}
82168224

82178225
if (Subtarget->isAmdPalOS() || Subtarget->isMesa3DOS()) {
8226+
if (Subtarget->has64BitLiterals()) {
8227+
SDValue Addr = DAG.getTargetGlobalAddress(
8228+
GV, DL, MVT::i64, GSD->getOffset(), SIInstrInfo::MO_ABS64);
8229+
return SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B64, DL, MVT::i64, Addr),
8230+
0);
8231+
}
8232+
82188233
SDValue AddrLo = DAG.getTargetGlobalAddress(
82198234
GV, DL, MVT::i32, GSD->getOffset(), SIInstrInfo::MO_ABS32_LO);
82208235
AddrLo = {DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, AddrLo), 0};

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp‎

Lines changed: 29 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2498,6 +2498,25 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
24982498
MI.eraseFromParent();
24992499
break;
25002500
}
2501+
case AMDGPU::SI_PC_ADD_REL_OFFSET64: {
2502+
MachineFunction &MF = *MBB.getParent();
2503+
Register Reg = MI.getOperand(0).getReg();
2504+
MachineOperand Op = MI.getOperand(1);
2505+
2506+
// Create a bundle so these instructions won't be re-ordered by the
2507+
// post-RA scheduler.
2508+
MIBundleBuilder Bundler(MBB, MI);
2509+
Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_GETPC_B64), Reg));
2510+
if (Op.isGlobal())
2511+
Op.setOffset(Op.getOffset() + 4);
2512+
Bundler.append(
2513+
BuildMI(MF, DL, get(AMDGPU::S_ADD_U64), Reg).addReg(Reg).add(Op));
2514+
2515+
finalizeBundle(MBB, Bundler.begin());
2516+
2517+
MI.eraseFromParent();
2518+
break;
2519+
}
25012520
case AMDGPU::ENTER_STRICT_WWM: {
25022521
// This only gets its own opcode so that SIPreAllocateWWMRegs can tell when
25032522
// Whole Wave Mode is entered.
@@ -9315,13 +9334,16 @@ SIInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
93159334
ArrayRef<std::pair<unsigned, const char *>>
93169335
SIInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
93179336
static const std::pair<unsigned, const char *> TargetFlags[] = {
9318-
{ MO_GOTPCREL, "amdgpu-gotprel" },
9319-
{ MO_GOTPCREL32_LO, "amdgpu-gotprel32-lo" },
9320-
{ MO_GOTPCREL32_HI, "amdgpu-gotprel32-hi" },
9321-
{ MO_REL32_LO, "amdgpu-rel32-lo" },
9322-
{ MO_REL32_HI, "amdgpu-rel32-hi" },
9323-
{ MO_ABS32_LO, "amdgpu-abs32-lo" },
9324-
{ MO_ABS32_HI, "amdgpu-abs32-hi" },
9337+
{MO_GOTPCREL, "amdgpu-gotprel"},
9338+
{MO_GOTPCREL32_LO, "amdgpu-gotprel32-lo"},
9339+
{MO_GOTPCREL32_HI, "amdgpu-gotprel32-hi"},
9340+
{MO_GOTPCREL64, "amdgpu-gotprel64"},
9341+
{MO_REL32_LO, "amdgpu-rel32-lo"},
9342+
{MO_REL32_HI, "amdgpu-rel32-hi"},
9343+
{MO_REL64, "amdgpu-rel64"},
9344+
{MO_ABS32_LO, "amdgpu-abs32-lo"},
9345+
{MO_ABS32_HI, "amdgpu-abs32-hi"},
9346+
{MO_ABS64, "amdgpu-abs64"},
93259347
};
93269348

93279349
return ArrayRef(TargetFlags);

0 commit comments

Comments
 (0)