AMDGPU: Stop using the wavemask register class for SCC cross class copies (#161801)

arsenm · web-flow · commit 1cc9a8c1272f · 2025-10-07T00:44:45.000+09:00
SCC should be copied to a 32-bit SGPR. Using a wave mask doesn't make
sense.
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1118,9 +1118,7 @@ SIRegisterInfo::getPointerRegClass(unsigned Kind) const {
 
 const TargetRegisterClass *
 SIRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
-  if (RC == &AMDGPU::SCC_CLASSRegClass)
-    return getWaveMaskRegClass();
-  return RC;
+  return RC == &AMDGPU::SCC_CLASSRegClass ? &AMDGPU::SReg_32RegClass : RC;
 }
 
 static unsigned getNumSubRegsForSpillOp(const MachineInstr &MI,

Original file line number	Diff line number	Diff line change
`@@ -1118,9 +1118,7 @@ SIRegisterInfo::getPointerRegClass(unsigned Kind) const {`
`1118`	`1118`
`1119`	`1119`	`const TargetRegisterClass *`
`1120`	`1120`	`SIRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {`
`1121`		`- if (RC == &AMDGPU::SCC_CLASSRegClass)`
`1122`		`- return getWaveMaskRegClass();`
`1123`		`- return RC;`
	`1121`	`+ return RC == &AMDGPU::SCC_CLASSRegClass ? &AMDGPU::SReg_32RegClass : RC;`
`1124`	`1122`	`}`
`1125`	`1123`
`1126`	`1124`	`static unsigned getNumSubRegsForSpillOp(const MachineInstr &MI,`