[DAG] Add fneg test.

Author: harrisonGPU

llvm/test/CodeGen/AMDGPU/freeze-binary.ll

@@ -1,30 +1,40 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefix GFX11
-define float @freeze_fadd(float %input) nounwind {
-; GFX11-LABEL: freeze_fadd:
+
+define float @freeze_fneg(float %input) nounwind {
+; GFX11-LABEL: freeze_fneg:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_f32_e32 v0, 2.0, v0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 entry:
-  %x = fadd reassoc nsz arcp contract afn float %input, 1.000000e+00
+  %x = fneg reassoc nsz arcp contract afn float %input
   %y = freeze float %x
-  %z = fadd reassoc nsz arcp contract afn float %y, 1.000000e+00
+  %z = fneg reassoc nsz arcp contract afn float %y
   ret float %z
 }
 
-define float @freeze_fadd_nnan(float %input) nounwind {
-; GFX11-LABEL: freeze_fadd_nnan:
+define <8 x float> @freeze_fneg_vec(<8 x float> %input) nounwind {
+; GFX11-LABEL: freeze_fneg_vec:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_f32_e32 v0, 1.0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v0, 1.0, v0
 ; GFX11-NEXT:    s_setpc_b64 s[30:31]
 entry:
-  %x = fadd nnan contract float %input, 1.000000e+00
+  %x = fneg <8 x float> %input
+  %y = freeze <8 x float> %x
+  %z = fneg <8 x float> %y
+  ret <8 x float> %z
+}
+
+define float @freeze_fadd(float %input) nounwind {
+; GFX11-LABEL: freeze_fadd:
+; GFX11:       ; %bb.0: ; %entry
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_add_f32_e32 v0, 2.0, v0
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+entry:
+  %x = fadd reassoc nsz arcp contract afn float %input, 1.000000e+00
   %y = freeze float %x
-  %z = fadd nnan contract float %y, 1.000000e+00
+  %z = fadd reassoc nsz arcp contract afn float %y, 1.000000e+00
   ret float %z
 }
 
@@ -57,21 +67,6 @@ entry:
   ret float %z
 }
 
-define float @freeze_fsub_nnan(float %input) nounwind {
-; GFX11-LABEL: freeze_fsub_nnan:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_subrev_f32_e32 v0, 1.0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_subrev_f32_e32 v0, 1.0, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-entry:
-  %x = fsub nnan contract float %input, 1.000000e+00
-  %y = freeze float %x
-  %z = fsub nnan contract float %y, 1.000000e+00
-  ret float %z
-}
-
 define <4 x float> @freeze_fsub_vec(<4 x float> %input) nounwind {
 ; GFX11-LABEL: freeze_fsub_vec:
 ; GFX11:       ; %bb.0: ; %entry
@@ -99,21 +94,6 @@ entry:
   ret float %z
 }
 
-define float @freeze_fmul_nnan(float %input) nounwind {
-; GFX11-LABEL: freeze_fmul_nnan:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_add_f32_e32 v0, v0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_add_f32_e32 v0, v0, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-entry:
-  %x = fmul nnan contract float %input, 2.000000e+00
-  %y = freeze float %x
-  %z = fmul nnan contract float %y, 2.000000e+00
-  ret float %z
-}
-
 define <8 x float> @freeze_fmul_vec(<8 x float> %input) nounwind {
 ; GFX11-LABEL: freeze_fmul_vec:
 ; GFX11:       ; %bb.0: ; %entry
@@ -143,21 +123,6 @@ entry:
   ret float %z
 }
 
-define float @freeze_fdiv_nnan(float %input) nounwind {
-; GFX11-LABEL: freeze_fdiv_nnan:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f32_e32 v0, 0.5, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f32_e32 v0, 0.5, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-entry:
-  %x = fdiv nnan contract float %input, 2.000000e+00
-  %y = freeze float %x
-  %z = fdiv nnan contract float %y, 2.000000e+00
-  ret float %z
-}
-
 define <8 x float> @freeze_fdiv_vec(<8 x float> %input) nounwind {
 ; GFX11-LABEL: freeze_fdiv_vec:
 ; GFX11:       ; %bb.0: ; %entry
@@ -195,30 +160,6 @@ entry:
   ret float %z
 }
 
-define float @freeze_frem_nnan(float %input) nounwind {
-; GFX11-LABEL: freeze_frem_nnan:
-; GFX11:       ; %bb.0: ; %entry
-; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT:    v_mul_f32_e32 v1, 0.5, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX11-NEXT:    v_fma_f32 v1, -2.0, v1, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, v0
-; GFX11-NEXT:    v_mul_f32_e32 v2, 0.5, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_trunc_f32_e32 v2, v2
-; GFX11-NEXT:    v_fmac_f32_e32 v1, -2.0, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_bfi_b32 v0, 0x7fffffff, v1, v0
-; GFX11-NEXT:    s_setpc_b64 s[30:31]
-entry:
-  %x = frem nnan contract float %input, 2.000000e+00
-  %y = freeze float %x
-  %z = frem nnan contract float %y, 2.000000e+00
-  ret float %z
-}
-
 define <8 x float> @freeze_frem_vec(<8 x float> %input) nounwind {
 ; GFX11-LABEL: freeze_frem_vec:
 ; GFX11:       ; %bb.0: ; %entry