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llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -11301,21 +11301,21 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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break;
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}
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11304+
SDValue GlueOp = CompNode.getValue(1);
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if (Subtarget.isISA3_1()) {
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SDValue SubRegIdx = DAG.getTargetConstant(Bitx, dl, MVT::i32);
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SDValue CR6Reg = DAG.getRegister(PPC::CR6, MVT::i32);
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SDValue CRBit =
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SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, MVT::i1,
11309-
CR6Reg, SubRegIdx, CompNode.getValue(1)),
11310-
0);
11310+
CR6Reg, SubRegIdx, GlueOp), 0);
1131111311
return DAG.getNode(SetOp, dl, MVT::i32, CRBit);
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}
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// Now that we have the comparison, emit a copy from the CR to a GPR.
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// This is flagged to the above dot comparison.
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SDValue Flags =
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DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
11318-
DAG.getRegister(PPC::CR6, MVT::i32), CompNode.getValue(1));
11318+
DAG.getRegister(PPC::CR6, MVT::i32), GlueOp);
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1132011320
// Shift the bit into the low position.
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Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,

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