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EbinJose2002EbinJose2002
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FEAT :
 - Formatted the code as per clang format
1 parent 204cf4b commit 1dfb08c

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-80
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‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp‎

Lines changed: 78 additions & 80 deletions
Original file line numberDiff line numberDiff line change
@@ -731,10 +731,9 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
731731
? SPIRV::OpIAddCarryV
732732
: SPIRV::OpIAddCarryS);
733733
case TargetOpcode::G_SADDO:
734-
return selectSignedOverflowArith(ResVReg, ResType, I,
735-
ResType->getOpcode() == SPIRV::OpTypeVector
736-
? true
737-
: false);
734+
return selectSignedOverflowArith(
735+
ResVReg, ResType, I,
736+
ResType->getOpcode() == SPIRV::OpTypeVector ? true : false);
738737
case TargetOpcode::G_USUBO:
739738
return selectOverflowArith(ResVReg, ResType, I,
740739
ResType->getOpcode() == SPIRV::OpTypeVector
@@ -1383,15 +1382,14 @@ bool SPIRVInstructionSelector::selectOverflowArith(Register ResVReg,
13831382
.constrainAllUses(TII, TRI, RBI);
13841383
}
13851384

1386-
bool SPIRVInstructionSelector::selectSignedOverflowArith(Register ResVReg,
1387-
const SPIRVType *ResType,
1388-
MachineInstr &I,
1389-
bool isVector) const {
1390-
1385+
bool SPIRVInstructionSelector::selectSignedOverflowArith(
1386+
Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
1387+
bool isVector) const {
13911388

1392-
//Checking overflow based on the logic that if two operands are positive and the sum is
1393-
//less than one of the operands then an overflow occured. Likewise if two operands are
1394-
//negative and if sum is greater than one operand then also overflow occured.
1389+
// Checking overflow based on the logic that if two operands are positive and
1390+
// the sum is less than one of the operands then an overflow occured. Likewise
1391+
// if two operands are negative and if sum is greater than one operand then
1392+
// also overflow occured.
13951393

13961394
Type *ResTy = nullptr;
13971395
StringRef ResName;
@@ -1401,14 +1399,14 @@ bool SPIRVInstructionSelector::selectSignedOverflowArith(Register ResVReg,
14011399
"Not enough info to select the signed arithmetic instruction");
14021400
if (!ResTy || !ResTy->isStructTy())
14031401
report_fatal_error(
1404-
"Expect struct type result for the signed arithmetic instruction");
1405-
1402+
"Expect struct type result for the signed arithmetic instruction");
1403+
14061404
StructType *ResStructTy = cast<StructType>(ResTy);
14071405
Type *ResElemTy = ResStructTy->getElementType(0);
14081406
Type *OverflowTy = ResStructTy->getElementType(1);
14091407
ResTy = StructType::get(ResElemTy, OverflowTy);
14101408
SPIRVType *StructType = GR.getOrCreateSPIRVType(
1411-
ResTy, MIRBuilder, SPIRV::AccessQualifier::ReadWrite, false);
1409+
ResTy, MIRBuilder, SPIRV::AccessQualifier::ReadWrite, false);
14121410
if (!StructType) {
14131411
report_fatal_error("Failed to create SPIR-V type for struct");
14141412
}
@@ -1420,16 +1418,18 @@ bool SPIRVInstructionSelector::selectSignedOverflowArith(Register ResVReg,
14201418
Register ZeroReg = buildZerosVal(ResType, I);
14211419
Register StructVReg = MRI->createGenericVirtualRegister(LLT::scalar(64));
14221420
MRI->setRegClass(StructVReg, &SPIRV::IDRegClass);
1423-
1421+
14241422
if (ResName.size() > 0)
14251423
buildOpName(StructVReg, ResName, MIRBuilder);
1426-
1424+
14271425
MachineBasicBlock &BB = *I.getParent();
14281426
Register SumVReg = MRI->createGenericVirtualRegister(LLT::scalar(64));
14291427
MRI->setRegClass(SumVReg, &SPIRV::IDRegClass);
1430-
SPIRVType *IntType = GR.getOrCreateSPIRVType(ResElemTy,MIRBuilder,SPIRV::AccessQualifier::ReadWrite,true);
1428+
SPIRVType *IntType = GR.getOrCreateSPIRVType(
1429+
ResElemTy, MIRBuilder, SPIRV::AccessQualifier::ReadWrite, true);
14311430

1432-
auto SumMIB = BuildMI(BB, MIRBuilder.getInsertPt(), I.getDebugLoc(), TII.get(isVector ? SPIRV::OpIAddV : SPIRV::OpIAddS))
1431+
auto SumMIB = BuildMI(BB, MIRBuilder.getInsertPt(), I.getDebugLoc(),
1432+
TII.get(isVector ? SPIRV::OpIAddV : SPIRV::OpIAddS))
14331433
.addDef(SumVReg)
14341434
.addUse(GR.getSPIRVTypeID(IntType));
14351435
for (unsigned i = I.getNumDefs(); i < I.getNumOperands(); ++i)
@@ -1450,32 +1450,32 @@ bool SPIRVInstructionSelector::selectSignedOverflowArith(Register ResVReg,
14501450
MRI->setRegClass(posOverflow, &SPIRV::IDRegClass);
14511451
Register posOverflowCheck = MRI->createGenericVirtualRegister(LLT::scalar(1));
14521452
MRI->setRegClass(posOverflowCheck, &SPIRV::IDRegClass);
1453-
1453+
14541454
BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSGreaterThan))
1455-
.addDef(posCheck1)
1456-
.addUse(GR.getSPIRVTypeID(BoolType))
1457-
.addUse(I.getOperand(i).getReg())
1458-
.addUse(ZeroReg);
1455+
.addDef(posCheck1)
1456+
.addUse(GR.getSPIRVTypeID(BoolType))
1457+
.addUse(I.getOperand(i).getReg())
1458+
.addUse(ZeroReg);
14591459
BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSGreaterThan))
1460-
.addDef(posCheck2)
1461-
.addUse(GR.getSPIRVTypeID(BoolType))
1462-
.addUse(I.getOperand(i+1).getReg())
1463-
.addUse(ZeroReg);
1460+
.addDef(posCheck2)
1461+
.addUse(GR.getSPIRVTypeID(BoolType))
1462+
.addUse(I.getOperand(i + 1).getReg())
1463+
.addUse(ZeroReg);
14641464
BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSLessThan))
1465-
.addDef(posCheck3)
1466-
.addUse(GR.getSPIRVTypeID(BoolType))
1467-
.addUse(SumVReg)
1468-
.addUse(I.getOperand(i+1).getReg());
1465+
.addDef(posCheck3)
1466+
.addUse(GR.getSPIRVTypeID(BoolType))
1467+
.addUse(SumVReg)
1468+
.addUse(I.getOperand(i + 1).getReg());
14691469
BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpLogicalAnd))
1470-
.addDef(posOverflow)
1471-
.addUse(GR.getSPIRVTypeID(BoolType))
1472-
.addUse(posCheck1)
1473-
.addUse(posCheck2);
1470+
.addDef(posOverflow)
1471+
.addUse(GR.getSPIRVTypeID(BoolType))
1472+
.addUse(posCheck1)
1473+
.addUse(posCheck2);
14741474
BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpLogicalAnd))
1475-
.addDef(posOverflowCheck)
1476-
.addUse(GR.getSPIRVTypeID(BoolType))
1477-
.addUse(posOverflow)
1478-
.addUse(posCheck3);
1475+
.addDef(posOverflowCheck)
1476+
.addUse(GR.getSPIRVTypeID(BoolType))
1477+
.addUse(posOverflow)
1478+
.addUse(posCheck3);
14791479

14801480
Register negCheck1 = MRI->createGenericVirtualRegister(LLT::scalar(1));
14811481
MRI->setRegClass(negCheck1, &SPIRV::IDRegClass);
@@ -1487,54 +1487,55 @@ bool SPIRVInstructionSelector::selectSignedOverflowArith(Register ResVReg,
14871487
MRI->setRegClass(negOverflow, &SPIRV::IDRegClass);
14881488
Register negOverflowCheck = MRI->createGenericVirtualRegister(LLT::scalar(1));
14891489
MRI->setRegClass(negOverflowCheck, &SPIRV::IDRegClass);
1490-
1490+
14911491
BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSLessThan))
1492-
.addDef(negCheck1)
1493-
.addUse(GR.getSPIRVTypeID(BoolType))
1494-
.addUse(I.getOperand(i).getReg())
1495-
.addUse(ZeroReg);
1492+
.addDef(negCheck1)
1493+
.addUse(GR.getSPIRVTypeID(BoolType))
1494+
.addUse(I.getOperand(i).getReg())
1495+
.addUse(ZeroReg);
14961496
BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSLessThan))
1497-
.addDef(negCheck2)
1498-
.addUse(GR.getSPIRVTypeID(BoolType))
1499-
.addUse(I.getOperand(i+1).getReg())
1500-
.addUse(ZeroReg);
1497+
.addDef(negCheck2)
1498+
.addUse(GR.getSPIRVTypeID(BoolType))
1499+
.addUse(I.getOperand(i + 1).getReg())
1500+
.addUse(ZeroReg);
15011501
BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSGreaterThan))
1502-
.addDef(negCheck3)
1503-
.addUse(GR.getSPIRVTypeID(BoolType))
1504-
.addUse(SumVReg)
1505-
.addUse(I.getOperand(i+1).getReg());
1502+
.addDef(negCheck3)
1503+
.addUse(GR.getSPIRVTypeID(BoolType))
1504+
.addUse(SumVReg)
1505+
.addUse(I.getOperand(i + 1).getReg());
15061506
BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpLogicalAnd))
1507-
.addDef(negOverflow)
1508-
.addUse(GR.getSPIRVTypeID(BoolType))
1509-
.addUse(negCheck1)
1510-
.addUse(negCheck2);
1507+
.addDef(negOverflow)
1508+
.addUse(GR.getSPIRVTypeID(BoolType))
1509+
.addUse(negCheck1)
1510+
.addUse(negCheck2);
15111511
BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpLogicalAnd))
1512-
.addDef(negOverflowCheck)
1513-
.addUse(GR.getSPIRVTypeID(BoolType))
1514-
.addUse(negOverflow)
1515-
.addUse(negCheck3);
1512+
.addDef(negOverflowCheck)
1513+
.addUse(GR.getSPIRVTypeID(BoolType))
1514+
.addUse(negOverflow)
1515+
.addUse(negCheck3);
15161516

15171517
BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpLogicalOr))
1518-
.addDef(OverflowVReg)
1519-
.addUse(GR.getSPIRVTypeID(BoolType))
1520-
.addUse(negOverflowCheck)
1521-
.addUse(posOverflowCheck);
1522-
1518+
.addDef(OverflowVReg)
1519+
.addUse(GR.getSPIRVTypeID(BoolType))
1520+
.addUse(negOverflowCheck)
1521+
.addUse(posOverflowCheck);
1522+
15231523
// Construct the result struct containing sum and overflow flag
15241524
BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeConstruct))
1525-
.addDef(StructVReg)
1526-
.addUse(GR.getSPIRVTypeID(StructType))
1527-
.addUse(SumVReg)
1528-
.addUse(OverflowVReg);
1525+
.addDef(StructVReg)
1526+
.addUse(GR.getSPIRVTypeID(StructType))
1527+
.addUse(SumVReg)
1528+
.addUse(OverflowVReg);
15291529

15301530
Register HigherVReg = MRI->createGenericVirtualRegister(LLT::scalar(64));
15311531
MRI->setRegClass(HigherVReg, &SPIRV::iIDRegClass);
1532-
1532+
15331533
for (unsigned i = 0; i < I.getNumDefs(); ++i) {
15341534
auto MIB =
15351535
BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract))
15361536
.addDef(i == 1 ? HigherVReg : I.getOperand(i).getReg())
1537-
.addUse(i == 1 ? GR.getSPIRVTypeID(BoolType) : GR.getSPIRVTypeID(ResType))
1537+
.addUse(i == 1 ? GR.getSPIRVTypeID(BoolType)
1538+
: GR.getSPIRVTypeID(ResType))
15381539
.addUse(StructVReg)
15391540
.addImm(i);
15401541
Result &= MIB.constrainAllUses(TII, TRI, RBI);
@@ -1548,15 +1549,12 @@ bool SPIRVInstructionSelector::selectSignedOverflowArith(Register ResVReg,
15481549
.addUse(GR.getSPIRVTypeID(BoolType));
15491550

15501551
BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpLogicalNotEqual))
1551-
.addDef(I.getOperand(1).getReg())
1552-
.addUse(BoolTypeReg)
1553-
.addUse(HigherVReg)
1554-
.addUse(FalseReg)
1555-
.constrainAllUses(TII, TRI, RBI);
1552+
.addDef(I.getOperand(1).getReg())
1553+
.addUse(BoolTypeReg)
1554+
.addUse(HigherVReg)
1555+
.addUse(FalseReg)
1556+
.constrainAllUses(TII, TRI, RBI);
15561557
return true;
1557-
1558-
1559-
15601558
}
15611559

15621560
bool SPIRVInstructionSelector::selectAtomicCmpXchg(Register ResVReg,

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