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SelectionDAG: Support FMINIMUMNUM and FMINIMUM in combineMinNumMaxNumImpl
We also use `isOperationLegal` instead of `isOperationLegalOrCustom`, as `Custom` implemention of these FMAX/FMIN operation normally much more expensive than just 2 fcmp operations.
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6 files changed

+256
-361
lines changed

6 files changed

+256
-361
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp‎

Lines changed: 25 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -11516,15 +11516,24 @@ static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS,
1151611516
case ISD::SETLE:
1151711517
case ISD::SETULT:
1151811518
case ISD::SETULE: {
11519-
// Since it's known never nan to get here already, either fminnum or
11520-
// fminnum_ieee are OK. Try the ieee version first, since it's fminnum is
11521-
// expanded in terms of it.
11519+
// Since it's known never nan to get here already, either fminimumnum,
11520+
// fminimum, fminnum, or fminnum_ieee are OK. Try the ieee version first,
11521+
// since it's fminnum is expanded in terms of it.
11522+
unsigned IEEE2019NumOpcode =
11523+
(LHS == True) ? ISD::FMINIMUMNUM : ISD::FMAXIMUMNUM;
11524+
if (TLI.isOperationLegal(IEEE2019NumOpcode, VT))
11525+
return DAG.getNode(IEEE2019NumOpcode, DL, VT, LHS, RHS);
11526+
11527+
unsigned IEEE2019Opcode = (LHS == True) ? ISD::FMINIMUM : ISD::FMAXIMUM;
11528+
if (TLI.isOperationLegal(IEEE2019Opcode, VT))
11529+
return DAG.getNode(IEEE2019Opcode, DL, VT, LHS, RHS);
11530+
1152211531
unsigned IEEEOpcode = (LHS == True) ? ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE;
11523-
if (TLI.isOperationLegalOrCustom(IEEEOpcode, VT))
11532+
if (TLI.isOperationLegal(IEEEOpcode, VT))
1152411533
return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS);
1152511534

1152611535
unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM;
11527-
if (TLI.isOperationLegalOrCustom(Opcode, TransformVT))
11536+
if (TLI.isOperationLegal(Opcode, TransformVT))
1152811537
return DAG.getNode(Opcode, DL, VT, LHS, RHS);
1152911538
return SDValue();
1153011539
}
@@ -11534,12 +11543,21 @@ static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS,
1153411543
case ISD::SETGE:
1153511544
case ISD::SETUGT:
1153611545
case ISD::SETUGE: {
11546+
unsigned IEEE2019NumOpcode =
11547+
(LHS == True) ? ISD::FMAXIMUMNUM : ISD::FMINIMUMNUM;
11548+
if (TLI.isOperationLegal(IEEE2019NumOpcode, VT))
11549+
return DAG.getNode(IEEE2019NumOpcode, DL, VT, LHS, RHS);
11550+
11551+
unsigned IEEE2019Opcode = (LHS == True) ? ISD::FMAXIMUM : ISD::FMINIMUM;
11552+
if (TLI.isOperationLegal(IEEE2019Opcode, VT))
11553+
return DAG.getNode(IEEE2019Opcode, DL, VT, LHS, RHS);
11554+
1153711555
unsigned IEEEOpcode = (LHS == True) ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE;
11538-
if (TLI.isOperationLegalOrCustom(IEEEOpcode, VT))
11556+
if (TLI.isOperationLegal(IEEEOpcode, VT))
1153911557
return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS);
1154011558

1154111559
unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM;
11542-
if (TLI.isOperationLegalOrCustom(Opcode, TransformVT))
11560+
if (TLI.isOperationLegal(Opcode, TransformVT))
1154311561
return DAG.getNode(Opcode, DL, VT, LHS, RHS);
1154411562
return SDValue();
1154511563
}

‎llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll‎

Lines changed: 30 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -119,7 +119,7 @@ define float @v_test_fmin_legacy_ule_f32_nnan_nsz_flag(float %a, float %b) {
119119
; GFX12-NEXT: s_wait_samplecnt 0x0
120120
; GFX12-NEXT: s_wait_bvhcnt 0x0
121121
; GFX12-NEXT: s_wait_kmcnt 0x0
122-
; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
122+
; GFX12-NEXT: v_minimum_f32 v0, v0, v1
123123
; GFX12-NEXT: s_setpc_b64 s[30:31]
124124
%cmp = fcmp ule float %a, %b
125125
%val = select nnan nsz i1 %cmp, float %a, float %b
@@ -236,7 +236,7 @@ define float @v_test_fmax_legacy_uge_f32_nnan_nsz_flag(float %a, float %b) {
236236
; GFX12-NEXT: s_wait_samplecnt 0x0
237237
; GFX12-NEXT: s_wait_bvhcnt 0x0
238238
; GFX12-NEXT: s_wait_kmcnt 0x0
239-
; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
239+
; GFX12-NEXT: v_maximum_f32 v0, v0, v1
240240
; GFX12-NEXT: s_setpc_b64 s[30:31]
241241
%cmp = fcmp uge float %a, %b
242242
%val = select nnan nsz i1 %cmp, float %a, float %b
@@ -693,7 +693,7 @@ define half @v_test_fmin_legacy_ule_f16_nnan_nsz_flag(half %a, half %b) {
693693
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
694694
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
695695
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
696-
; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
696+
; GFX12-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v1.l
697697
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
698698
;
699699
; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_f16_nnan_nsz_flag:
@@ -703,7 +703,7 @@ define half @v_test_fmin_legacy_ule_f16_nnan_nsz_flag(half %a, half %b) {
703703
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
704704
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
705705
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
706-
; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
706+
; GFX12-FAKE16-NEXT: v_minimum_f16 v0, v0, v1
707707
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
708708
%cmp = fcmp ule half %a, %b
709709
%val = select nnan nsz i1 %cmp, half %a, half %b
@@ -872,7 +872,7 @@ define half @v_test_fmax_legacy_uge_f16_nnan_nsz_flag(half %a, half %b) {
872872
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
873873
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
874874
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
875-
; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
875+
; GFX12-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v1.l
876876
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
877877
;
878878
; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_f16_nnan_nsz_flag:
@@ -882,7 +882,7 @@ define half @v_test_fmax_legacy_uge_f16_nnan_nsz_flag(half %a, half %b) {
882882
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
883883
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
884884
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
885-
; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
885+
; GFX12-FAKE16-NEXT: v_maximum_f16 v0, v0, v1
886886
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
887887
%cmp = fcmp uge half %a, %b
888888
%val = select nnan nsz i1 %cmp, half %a, half %b
@@ -1122,7 +1122,7 @@ define <2 x half> @v_test_fmin_legacy_ule_v2f16_nnan_nsz_flag(<2 x half> %a, <2
11221122
; GFX12-NEXT: s_wait_samplecnt 0x0
11231123
; GFX12-NEXT: s_wait_bvhcnt 0x0
11241124
; GFX12-NEXT: s_wait_kmcnt 0x0
1125-
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v1
1125+
; GFX12-NEXT: v_pk_minimum_f16 v0, v0, v1
11261126
; GFX12-NEXT: s_setpc_b64 s[30:31]
11271127
%cmp = fcmp ule <2 x half> %a, %b
11281128
%val = select nnan nsz <2 x i1> %cmp, <2 x half> %a, <2 x half> %b
@@ -1362,7 +1362,7 @@ define <2 x half> @v_test_fmax_legacy_uge_v2f16_nnan_nsz_flag(<2 x half> %a, <2
13621362
; GFX12-NEXT: s_wait_samplecnt 0x0
13631363
; GFX12-NEXT: s_wait_bvhcnt 0x0
13641364
; GFX12-NEXT: s_wait_kmcnt 0x0
1365-
; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v1
1365+
; GFX12-NEXT: v_pk_maximum_f16 v0, v0, v1
13661366
; GFX12-NEXT: s_setpc_b64 s[30:31]
13671367
%cmp = fcmp uge <2 x half> %a, %b
13681368
%val = select nnan nsz <2 x i1> %cmp, <2 x half> %a, <2 x half> %b
@@ -1692,8 +1692,12 @@ define <4 x half> @v_test_fmin_legacy_ule_v4f16_nnan_nsz_flag(<4 x half> %a, <4
16921692
; GFX9-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_nsz_flag:
16931693
; GFX9: ; %bb.0:
16941694
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1695+
; GFX9-NEXT: v_pk_max_f16 v2, v2, v2
1696+
; GFX9-NEXT: v_pk_max_f16 v0, v0, v0
16951697
; GFX9-NEXT: v_pk_min_f16 v0, v0, v2
1696-
; GFX9-NEXT: v_pk_min_f16 v1, v1, v3
1698+
; GFX9-NEXT: v_pk_max_f16 v2, v3, v3
1699+
; GFX9-NEXT: v_pk_max_f16 v1, v1, v1
1700+
; GFX9-NEXT: v_pk_min_f16 v1, v1, v2
16971701
; GFX9-NEXT: s_setpc_b64 s[30:31]
16981702
;
16991703
; GFX12-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_nsz_flag:
@@ -1703,6 +1707,11 @@ define <4 x half> @v_test_fmin_legacy_ule_v4f16_nnan_nsz_flag(<4 x half> %a, <4
17031707
; GFX12-NEXT: s_wait_samplecnt 0x0
17041708
; GFX12-NEXT: s_wait_bvhcnt 0x0
17051709
; GFX12-NEXT: s_wait_kmcnt 0x0
1710+
; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
1711+
; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
1712+
; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
1713+
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
1714+
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
17061715
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v2
17071716
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v3
17081717
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -2034,8 +2043,12 @@ define <4 x half> @v_test_fmax_legacy_uge_v4f16_nnan_nsz_flag(<4 x half> %a, <4
20342043
; GFX9-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_nsz_flag:
20352044
; GFX9: ; %bb.0:
20362045
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2046+
; GFX9-NEXT: v_pk_max_f16 v2, v2, v2
2047+
; GFX9-NEXT: v_pk_max_f16 v0, v0, v0
20372048
; GFX9-NEXT: v_pk_max_f16 v0, v0, v2
2038-
; GFX9-NEXT: v_pk_max_f16 v1, v1, v3
2049+
; GFX9-NEXT: v_pk_max_f16 v2, v3, v3
2050+
; GFX9-NEXT: v_pk_max_f16 v1, v1, v1
2051+
; GFX9-NEXT: v_pk_max_f16 v1, v1, v2
20392052
; GFX9-NEXT: s_setpc_b64 s[30:31]
20402053
;
20412054
; GFX12-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_nsz_flag:
@@ -2045,6 +2058,11 @@ define <4 x half> @v_test_fmax_legacy_uge_v4f16_nnan_nsz_flag(<4 x half> %a, <4
20452058
; GFX12-NEXT: s_wait_samplecnt 0x0
20462059
; GFX12-NEXT: s_wait_bvhcnt 0x0
20472060
; GFX12-NEXT: s_wait_kmcnt 0x0
2061+
; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
2062+
; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
2063+
; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
2064+
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
2065+
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
20482066
; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v2
20492067
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v3
20502068
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -2079,7 +2097,7 @@ define float @v_test_fmin_legacy_uge_f32_nsz_flag__nnan_srcs(float %arg0, float
20792097
; GFX12-NEXT: s_wait_kmcnt 0x0
20802098
; GFX12-NEXT: v_dual_add_f32 v0, v0, v0 :: v_dual_add_f32 v1, v1, v1
20812099
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
2082-
; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
2100+
; GFX12-NEXT: v_minimum_f32 v0, v0, v1
20832101
; GFX12-NEXT: s_setpc_b64 s[30:31]
20842102
%a = fadd nnan float %arg0, %arg0
20852103
%b = fadd nnan float %arg1, %arg1
@@ -2114,7 +2132,7 @@ define float @v_test_fmax_legacy_uge_f32_nsz_flag__nnan_srcs(float %arg0, float
21142132
; GFX12-NEXT: s_wait_kmcnt 0x0
21152133
; GFX12-NEXT: v_dual_add_f32 v0, v0, v0 :: v_dual_add_f32 v1, v1, v1
21162134
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
2117-
; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
2135+
; GFX12-NEXT: v_maximum_f32 v0, v0, v1
21182136
; GFX12-NEXT: s_setpc_b64 s[30:31]
21192137
%a = fadd nnan float %arg0, %arg0
21202138
%b = fadd nnan float %arg1, %arg1

‎llvm/test/CodeGen/WebAssembly/f32.ll‎

Lines changed: 11 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -229,13 +229,10 @@ define float @fminnum32_intrinsic(float %x, float %y) {
229229
; CHECK-LABEL: fminnum32_intrinsic:
230230
; CHECK: .functype fminnum32_intrinsic (f32, f32) -> (f32)
231231
; CHECK-NEXT: # %bb.0:
232-
; CHECK-NEXT: local.get $push5=, 0
233-
; CHECK-NEXT: local.get $push4=, 1
234-
; CHECK-NEXT: local.get $push3=, 0
235-
; CHECK-NEXT: local.get $push2=, 1
236-
; CHECK-NEXT: f32.lt $push0=, $pop3, $pop2
237-
; CHECK-NEXT: f32.select $push1=, $pop5, $pop4, $pop0
238-
; CHECK-NEXT: return $pop1
232+
; CHECK-NEXT: local.get $push2=, 0
233+
; CHECK-NEXT: local.get $push1=, 1
234+
; CHECK-NEXT: f32.min $push0=, $pop2, $pop1
235+
; CHECK-NEXT: return $pop0
239236
%a = call nnan float @llvm.minnum.f32(float %x, float %y)
240237
ret float %a
241238
}
@@ -282,13 +279,10 @@ define float @fmaxnum32_intrinsic(float %x, float %y) {
282279
; CHECK-LABEL: fmaxnum32_intrinsic:
283280
; CHECK: .functype fmaxnum32_intrinsic (f32, f32) -> (f32)
284281
; CHECK-NEXT: # %bb.0:
285-
; CHECK-NEXT: local.get $push5=, 0
286-
; CHECK-NEXT: local.get $push4=, 1
287-
; CHECK-NEXT: local.get $push3=, 0
288-
; CHECK-NEXT: local.get $push2=, 1
289-
; CHECK-NEXT: f32.gt $push0=, $pop3, $pop2
290-
; CHECK-NEXT: f32.select $push1=, $pop5, $pop4, $pop0
291-
; CHECK-NEXT: return $pop1
282+
; CHECK-NEXT: local.get $push2=, 0
283+
; CHECK-NEXT: local.get $push1=, 1
284+
; CHECK-NEXT: f32.max $push0=, $pop2, $pop1
285+
; CHECK-NEXT: return $pop0
292286
%a = call nnan float @llvm.maxnum.f32(float %x, float %y)
293287
ret float %a
294288
}
@@ -309,13 +303,10 @@ define float @fmaxnum32_zero_intrinsic(float %x) {
309303
; CHECK-LABEL: fmaxnum32_zero_intrinsic:
310304
; CHECK: .functype fmaxnum32_zero_intrinsic (f32) -> (f32)
311305
; CHECK-NEXT: # %bb.0:
312-
; CHECK-NEXT: local.get $push5=, 0
306+
; CHECK-NEXT: local.get $push2=, 0
313307
; CHECK-NEXT: f32.const $push0=, 0x0p0
314-
; CHECK-NEXT: local.get $push4=, 0
315-
; CHECK-NEXT: f32.const $push3=, 0x0p0
316-
; CHECK-NEXT: f32.gt $push1=, $pop4, $pop3
317-
; CHECK-NEXT: f32.select $push2=, $pop5, $pop0, $pop1
318-
; CHECK-NEXT: return $pop2
308+
; CHECK-NEXT: f32.max $push1=, $pop2, $pop0
309+
; CHECK-NEXT: return $pop1
319310
%a = call nnan float @llvm.maxnum.f32(float %x, float 0.0)
320311
ret float %a
321312
}

‎llvm/test/CodeGen/WebAssembly/f64.ll‎

Lines changed: 14 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -229,13 +229,10 @@ define double @fminnum64_intrinsic(double %x, double %y) {
229229
; CHECK-LABEL: fminnum64_intrinsic:
230230
; CHECK: .functype fminnum64_intrinsic (f64, f64) -> (f64)
231231
; CHECK-NEXT: # %bb.0:
232-
; CHECK-NEXT: local.get $push5=, 0
233-
; CHECK-NEXT: local.get $push4=, 1
234-
; CHECK-NEXT: local.get $push3=, 0
235-
; CHECK-NEXT: local.get $push2=, 1
236-
; CHECK-NEXT: f64.lt $push0=, $pop3, $pop2
237-
; CHECK-NEXT: f64.select $push1=, $pop5, $pop4, $pop0
238-
; CHECK-NEXT: return $pop1
232+
; CHECK-NEXT: local.get $push2=, 0
233+
; CHECK-NEXT: local.get $push1=, 1
234+
; CHECK-NEXT: f64.min $push0=, $pop2, $pop1
235+
; CHECK-NEXT: return $pop0
239236
%a = call nnan double @llvm.minnum.f64(double %x, double %y)
240237
ret double %a
241238
}
@@ -256,13 +253,10 @@ define double @fminnum64_zero_intrinsic(double %x) {
256253
; CHECK-LABEL: fminnum64_zero_intrinsic:
257254
; CHECK: .functype fminnum64_zero_intrinsic (f64) -> (f64)
258255
; CHECK-NEXT: # %bb.0:
259-
; CHECK-NEXT: local.get $push5=, 0
256+
; CHECK-NEXT: local.get $push2=, 0
260257
; CHECK-NEXT: f64.const $push0=, -0x0p0
261-
; CHECK-NEXT: local.get $push4=, 0
262-
; CHECK-NEXT: f64.const $push3=, -0x0p0
263-
; CHECK-NEXT: f64.lt $push1=, $pop4, $pop3
264-
; CHECK-NEXT: f64.select $push2=, $pop5, $pop0, $pop1
265-
; CHECK-NEXT: return $pop2
258+
; CHECK-NEXT: f64.min $push1=, $pop2, $pop0
259+
; CHECK-NEXT: return $pop1
266260
%a = call nnan double @llvm.minnum.f64(double %x, double -0.0)
267261
ret double %a
268262
}
@@ -297,13 +291,10 @@ define double@fmaxnum64_intrinsic(double %x, double %y) {
297291
; CHECK-LABEL: fmaxnum64_intrinsic:
298292
; CHECK: .functype fmaxnum64_intrinsic (f64, f64) -> (f64)
299293
; CHECK-NEXT: # %bb.0:
300-
; CHECK-NEXT: local.get $push5=, 0
301-
; CHECK-NEXT: local.get $push4=, 1
302-
; CHECK-NEXT: local.get $push3=, 0
303-
; CHECK-NEXT: local.get $push2=, 1
304-
; CHECK-NEXT: f64.gt $push0=, $pop3, $pop2
305-
; CHECK-NEXT: f64.select $push1=, $pop5, $pop4, $pop0
306-
; CHECK-NEXT: return $pop1
294+
; CHECK-NEXT: local.get $push2=, 0
295+
; CHECK-NEXT: local.get $push1=, 1
296+
; CHECK-NEXT: f64.max $push0=, $pop2, $pop1
297+
; CHECK-NEXT: return $pop0
307298
%a = call nnan double @llvm.maxnum.f64(double %x, double %y)
308299
ret double %a
309300
}
@@ -324,13 +315,10 @@ define double @fmaxnum64_zero_intrinsic(double %x) {
324315
; CHECK-LABEL: fmaxnum64_zero_intrinsic:
325316
; CHECK: .functype fmaxnum64_zero_intrinsic (f64) -> (f64)
326317
; CHECK-NEXT: # %bb.0:
327-
; CHECK-NEXT: local.get $push5=, 0
318+
; CHECK-NEXT: local.get $push2=, 0
328319
; CHECK-NEXT: f64.const $push0=, 0x0p0
329-
; CHECK-NEXT: local.get $push4=, 0
330-
; CHECK-NEXT: f64.const $push3=, 0x0p0
331-
; CHECK-NEXT: f64.gt $push1=, $pop4, $pop3
332-
; CHECK-NEXT: f64.select $push2=, $pop5, $pop0, $pop1
333-
; CHECK-NEXT: return $pop2
320+
; CHECK-NEXT: f64.max $push1=, $pop2, $pop0
321+
; CHECK-NEXT: return $pop1
334322
%a = call nnan double @llvm.maxnum.f64(double %x, double 0.0)
335323
ret double %a
336324
}

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