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1 parent c67ab47 commit 1e03d06Copy full SHA for 1e03d06
mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
@@ -589,10 +589,6 @@ LogicalResult SwitchOp::verify() {
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static_cast<int64_t>(getCaseDestinations().size())))
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return emitOpError("expects number of case values to match number of "
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"case destinations");
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- if (getBranchWeights() && getBranchWeights()->size() != getNumSuccessors())
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- return emitError("expects number of branch weights to match number of "
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- "successors: ")
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- << getBranchWeights()->size() << " vs " << getNumSuccessors();
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if (getCaseValues() &&
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getValue().getType() != getCaseValues()->getElementType())
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return emitError("expects case value type to match condition value type");
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