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MDevereauMDevereau
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[AArch64][InstCombine] Canonicalize whilelo intrinsic (#151553)
InstCombine llvm.aarch64.sve.whilelo to the generic LLVM llvm.get.active.lane.mask intrinsic
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‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp‎

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@@ -2747,6 +2747,15 @@ static std::optional<Instruction *> instCombineDMB(InstCombiner &IC,
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return std::nullopt;
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}
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static std::optional<Instruction *> instCombineWhilelo(InstCombiner &IC,
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IntrinsicInst &II) {
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return IC.replaceInstUsesWith(
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II,
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IC.Builder.CreateIntrinsic(Intrinsic::get_active_lane_mask,
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{II.getType(), II.getOperand(0)->getType()},
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{II.getOperand(0), II.getOperand(1)}));
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}
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static std::optional<Instruction *> instCombinePTrue(InstCombiner &IC,
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IntrinsicInst &II) {
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if (match(II.getOperand(0), m_ConstantInt<AArch64SVEPredPattern::all>()))
@@ -2883,6 +2892,8 @@ AArch64TTIImpl::instCombineIntrinsic(InstCombiner &IC,
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return instCombineSVEDupqLane(IC, II);
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case Intrinsic::aarch64_sve_insr:
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return instCombineSVEInsr(IC, II);
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case Intrinsic::aarch64_sve_whilelo:
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return instCombineWhilelo(IC, II);
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case Intrinsic::aarch64_sve_ptrue:
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return instCombinePTrue(IC, II);
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case Intrinsic::aarch64_sve_uxtb:

‎llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-whilelo.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -S -passes=instcombine < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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define <vscale x 2 x i1> @whilelo_nxv2i1.i32(i32 %a, i32 %b) {
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; CHECK-LABEL: define <vscale x 2 x i1> @whilelo_nxv2i1.i32(
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; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) {
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; CHECK-NEXT: [[MASK:%.*]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i32(i32 [[A]], i32 [[B]])
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; CHECK-NEXT: ret <vscale x 2 x i1> [[MASK]]
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;
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%mask = tail call <vscale x 2 x i1> @llvm.aarch64.sve.whilelo.nxv2i1.i32(i32 %a, i32 %b)
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ret <vscale x 2 x i1> %mask
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}
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define <vscale x 4 x i1> @whilelo_nxv4i1.i32(i32 %a, i32 %b) {
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; CHECK-LABEL: define <vscale x 4 x i1> @whilelo_nxv4i1.i32(
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; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) {
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; CHECK-NEXT: [[MASK:%.*]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 [[A]], i32 [[B]])
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; CHECK-NEXT: ret <vscale x 4 x i1> [[MASK]]
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;
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%mask = tail call <vscale x 4 x i1> @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32 %a, i32 %b)
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ret <vscale x 4 x i1> %mask
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}
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define <vscale x 8 x i1> @whilelo_nxv8i1.i32(i32 %a, i32 %b) {
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; CHECK-LABEL: define <vscale x 8 x i1> @whilelo_nxv8i1.i32(
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; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) {
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; CHECK-NEXT: [[MASK:%.*]] = call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i32(i32 [[A]], i32 [[B]])
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; CHECK-NEXT: ret <vscale x 8 x i1> [[MASK]]
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;
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%mask = tail call <vscale x 8 x i1> @llvm.aarch64.sve.whilelo.nxv8i1.i32(i32 %a, i32 %b)
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ret <vscale x 8 x i1> %mask
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}
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define <vscale x 16 x i1> @whilelo_nxv16i1.i32(i32 %a, i32 %b) {
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; CHECK-LABEL: define <vscale x 16 x i1> @whilelo_nxv16i1.i32(
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; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) {
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; CHECK-NEXT: [[MASK:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i32(i32 [[A]], i32 [[B]])
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; CHECK-NEXT: ret <vscale x 16 x i1> [[MASK]]
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;
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%mask = tail call <vscale x 16 x i1> @llvm.aarch64.sve.whilelo.nxv16i1.i32(i32 %a, i32 %b)
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ret <vscale x 16 x i1> %mask
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}
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define <vscale x 2 x i1> @whilelo_nxv2i1.i64(i64 %a, i64 %b) {
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; CHECK-LABEL: define <vscale x 2 x i1> @whilelo_nxv2i1.i64(
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; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) {
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; CHECK-NEXT: [[MASK:%.*]] = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 [[A]], i64 [[B]])
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; CHECK-NEXT: ret <vscale x 2 x i1> [[MASK]]
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;
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%mask = tail call <vscale x 2 x i1> @llvm.aarch64.sve.whilelo.nxv2i1.i64(i64 %a, i64 %b)
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ret <vscale x 2 x i1> %mask
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}
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define <vscale x 4 x i1> @whilelo_nxv4i1.i64(i64 %a, i64 %b) {
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; CHECK-LABEL: define <vscale x 4 x i1> @whilelo_nxv4i1.i64(
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; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) {
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; CHECK-NEXT: [[MASK:%.*]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[A]], i64 [[B]])
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; CHECK-NEXT: ret <vscale x 4 x i1> [[MASK]]
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;
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%mask = tail call <vscale x 4 x i1> @llvm.aarch64.sve.whilelo.nxv4i1.i64(i64 %a, i64 %b)
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ret <vscale x 4 x i1> %mask
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}
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define <vscale x 8 x i1> @whilelo_nxv8i1.i64(i64 %a, i64 %b) {
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; CHECK-LABEL: define <vscale x 8 x i1> @whilelo_nxv8i1.i64(
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; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) {
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; CHECK-NEXT: [[MASK:%.*]] = call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i64(i64 [[A]], i64 [[B]])
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; CHECK-NEXT: ret <vscale x 8 x i1> [[MASK]]
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;
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%mask = tail call <vscale x 8 x i1> @llvm.aarch64.sve.whilelo.nxv8i1.i64(i64 %a, i64 %b)
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ret <vscale x 8 x i1> %mask
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}
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define <vscale x 16 x i1> @whilelo_nxv16i1.i64(i64 %a, i64 %b) {
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; CHECK-LABEL: define <vscale x 16 x i1> @whilelo_nxv16i1.i64(
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; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) {
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; CHECK-NEXT: [[MASK:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[A]], i64 [[B]])
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; CHECK-NEXT: ret <vscale x 16 x i1> [[MASK]]
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;
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%mask = tail call <vscale x 16 x i1> @llvm.aarch64.sve.whilelo.nxv16i1.i64(i64 %a, i64 %b)
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ret <vscale x 16 x i1> %mask
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}
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define <vscale x 16 x i1> @whilelo_nxv16i1.i64_const() {
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; CHECK-LABEL: define <vscale x 16 x i1> @whilelo_nxv16i1.i64_const() {
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; CHECK-NEXT: [[MASK:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 16)
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; CHECK-NEXT: ret <vscale x 16 x i1> [[MASK]]
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;
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%mask = tail call <vscale x 16 x i1> @llvm.aarch64.sve.whilelo.nxv16i1.i64(i64 0, i64 16)
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ret <vscale x 16 x i1> %mask
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}
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define <vscale x 16 x i1> @whilelo_nxv16i1.i32_const() {
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; CHECK-LABEL: define <vscale x 16 x i1> @whilelo_nxv16i1.i32_const() {
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; CHECK-NEXT: [[MASK:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i32(i32 0, i32 16)
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; CHECK-NEXT: ret <vscale x 16 x i1> [[MASK]]
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;
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%mask = tail call <vscale x 16 x i1> @llvm.aarch64.sve.whilelo.nxv16i1.i32(i32 0, i32 16)
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ret <vscale x 16 x i1> %mask
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}

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