[InitUndef] Don't use largest super class (#107885)

The InitUndef pass currently uses the getLargestSuperClass() hook (which
is only used by that pass) to chose the register to initialize. This was done
to reduce the number of undef init pseudos needed, e.g. so that the vrnov0
regclass would use the same pseudo as v0. After #106744 we use a single
generic pseudo, so this is no longer necessary.

Author: nikic

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

@@ -1204,15 +1204,6 @@ class TargetRegisterInfo : public MCRegisterInfo {
     return false;
   }
 
-  /// Returns the Largest Super Class that is being initialized. There
-  /// should be a Pseudo Instruction implemented for the super class
-  /// that is being returned to ensure that Init Undef can apply the
-  /// initialization correctly.
-  virtual const TargetRegisterClass *
-  getLargestSuperClass(const TargetRegisterClass *RC) const {
-    llvm_unreachable("Unexpected target register class.");
-  }
-
   /// Returns if the architecture being targeted has the required Pseudo
   /// Instructions for initializing the register. By default this returns false,
   /// but where it is overriden for an architecture, the behaviour will be

llvm/lib/CodeGen/InitUndef.cpp

@@ -152,8 +152,7 @@ bool InitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI,
     if (Info.UsedLanes == Info.DefinedLanes)
       continue;
 
-    const TargetRegisterClass *TargetRegClass =
-        TRI->getLargestSuperClass(MRI->getRegClass(Reg));
+    const TargetRegisterClass *TargetRegClass = MRI->getRegClass(Reg);
 
     LaneBitmask NeedDef = Info.UsedLanes & ~Info.DefinedLanes;
 
@@ -172,8 +171,8 @@ bool InitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI,
     Register LatestReg = Reg;
     for (auto ind : SubRegIndexNeedInsert) {
       Changed = true;
-      const TargetRegisterClass *SubRegClass = TRI->getLargestSuperClass(
-          TRI->getSubRegisterClass(TargetRegClass, ind));
+      const TargetRegisterClass *SubRegClass =
+          TRI->getSubRegisterClass(TargetRegClass, ind);
       Register TmpInitSubReg = MRI->createVirtualRegister(SubRegClass);
       LLVM_DEBUG(dbgs() << "Register Class ID" << SubRegClass->getID() << "\n");
       BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(),
@@ -199,8 +198,7 @@ bool InitUndef::fixupIllOperand(MachineInstr *MI, MachineOperand &MO) {
       dbgs() << "Emitting PseudoInitUndef Instruction for implicit register "
              << printReg(MO.getReg()) << '\n');
 
-  const TargetRegisterClass *TargetRegClass =
-      TRI->getLargestSuperClass(MRI->getRegClass(MO.getReg()));
+  const TargetRegisterClass *TargetRegClass = MRI->getRegClass(MO.getReg());
   LLVM_DEBUG(dbgs() << "Register Class ID" << TargetRegClass->getID() << "\n");
   Register NewReg = MRI->createVirtualRegister(TargetRegClass);
   BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),

llvm/lib/Target/ARM/ARMBaseRegisterInfo.h

@@ -241,19 +241,6 @@ class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
 
   int getSEHRegNum(unsigned i) const { return getEncodingValue(i); }
 
-  const TargetRegisterClass *
-  getLargestSuperClass(const TargetRegisterClass *RC) const override {
-    if (ARM::MQPRRegClass.hasSubClassEq(RC))
-      return &ARM::MQPRRegClass;
-    if (ARM::SPRRegClass.hasSubClassEq(RC))
-      return &ARM::SPRRegClass;
-    if (ARM::DPR_VFP2RegClass.hasSubClassEq(RC))
-      return &ARM::DPR_VFP2RegClass;
-    if (ARM::GPRRegClass.hasSubClassEq(RC))
-      return &ARM::GPRRegClass;
-    return RC;
-  }
-
   bool doesRegClassHavePseudoInitUndef(
       const TargetRegisterClass *RC) const override {
     (void)RC;

llvm/lib/Target/RISCV/RISCVRegisterInfo.h

@@ -130,19 +130,6 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
                              const MachineFunction &MF, const VirtRegMap *VRM,
                              const LiveRegMatrix *Matrix) const override;
 
-  const TargetRegisterClass *
-  getLargestSuperClass(const TargetRegisterClass *RC) const override {
-    if (RISCV::VRM8RegClass.hasSubClassEq(RC))
-      return &RISCV::VRM8RegClass;
-    if (RISCV::VRM4RegClass.hasSubClassEq(RC))
-      return &RISCV::VRM4RegClass;
-    if (RISCV::VRM2RegClass.hasSubClassEq(RC))
-      return &RISCV::VRM2RegClass;
-    if (RISCV::VRRegClass.hasSubClassEq(RC))
-      return &RISCV::VRRegClass;
-    return RC;
-  }
-
   bool doesRegClassHavePseudoInitUndef(
       const TargetRegisterClass *RC) const override {
     return isVRRegClass(RC);