[DAGCombiner][RISCV] Don't propagate the exact flag from udiv/sdiv to urem/srem.

If we simplify a udiv/sdiv using the exact flag we shouldn't
propagate that simplifaction to any urem/srem that happens to
use the same operands. If the exact flag is wrong, the udiv/sdiv
will produce poison, but that doesn't mean we can make the urem/srem
simplify to 0.

Fixes #145360.

Author: topperc

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -4961,11 +4961,15 @@ SDValue DAGCombiner::visitSDIV(SDNode *N) {
     // (Dividend - (Quotient * Divisor).
     if (SDNode *RemNode = DAG.getNodeIfExists(ISD::SREM, N->getVTList(),
                                               { N0, N1 })) {
-      SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1);
-      SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
-      AddToWorklist(Mul.getNode());
-      AddToWorklist(Sub.getNode());
-      CombineTo(RemNode, Sub);
+      // If the udiv has the exact flag we shouldn't propagate it to the
+      // remainder node.
+      if (!N->getFlags().hasExact()) {
+        SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1);
+        SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
+        AddToWorklist(Mul.getNode());
+        AddToWorklist(Sub.getNode());
+        CombineTo(RemNode, Sub);
+      }
     }
     return V;
   }
@@ -5101,11 +5105,15 @@ SDValue DAGCombiner::visitUDIV(SDNode *N) {
     // (Dividend - (Quotient * Divisor).
     if (SDNode *RemNode = DAG.getNodeIfExists(ISD::UREM, N->getVTList(),
                                               { N0, N1 })) {
-      SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1);
-      SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
-      AddToWorklist(Mul.getNode());
-      AddToWorklist(Sub.getNode());
-      CombineTo(RemNode, Sub);
+      // If the udiv has the exact flag we shouldn't propagate it to the
+      // remainder node.
+      if (!N->getFlags().hasExact()) {
+        SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1);
+        SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
+        AddToWorklist(Mul.getNode());
+        AddToWorklist(Sub.getNode());
+        CombineTo(RemNode, Sub);
+      }
     }
     return V;
   }

llvm/test/CodeGen/RISCV/pr145360.ll

@@ -4,8 +4,13 @@
 define i32 @signed(i32 %0, ptr %1) {
 ; CHECK-LABEL: signed:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    sraiw a2, a0, 31
+; CHECK-NEXT:    srliw a2, a2, 24
+; CHECK-NEXT:    add a2, a0, a2
+; CHECK-NEXT:    andi a2, a2, -256
+; CHECK-NEXT:    subw a2, a0, a2
 ; CHECK-NEXT:    sraiw a0, a0, 8
-; CHECK-NEXT:    sw zero, 0(a1)
+; CHECK-NEXT:    sw a2, 0(a1)
 ; CHECK-NEXT:    ret
   %rem = srem i32 %0, 256
   store i32 %rem, ptr %1, align 4
@@ -16,11 +21,19 @@ define i32 @signed(i32 %0, ptr %1) {
 define i32 @unsigned(i32 %0, ptr %1) {
 ; CHECK-LABEL: unsigned:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    srliw a0, a0, 3
-; CHECK-NEXT:    lui a2, 699051
-; CHECK-NEXT:    addi a2, a2, -1365
-; CHECK-NEXT:    mulw a0, a0, a2
-; CHECK-NEXT:    sw zero, 0(a1)
+; CHECK-NEXT:    slli a2, a0, 32
+; CHECK-NEXT:    lui a3, 699051
+; CHECK-NEXT:    addi a3, a3, -1365
+; CHECK-NEXT:    slli a4, a3, 32
+; CHECK-NEXT:    mulhu a2, a2, a4
+; CHECK-NEXT:    srli a2, a2, 36
+; CHECK-NEXT:    slli a4, a2, 5
+; CHECK-NEXT:    slli a2, a2, 3
+; CHECK-NEXT:    subw a2, a2, a4
+; CHECK-NEXT:    srliw a4, a0, 3
+; CHECK-NEXT:    add a2, a0, a2
+; CHECK-NEXT:    mulw a0, a4, a3
+; CHECK-NEXT:    sw a2, 0(a1)
 ; CHECK-NEXT:    ret
   %rem = urem i32 %0, 24
   store i32 %rem, ptr %1, align 4