Address comments

Author: jaidTw

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

@@ -3511,7 +3511,6 @@ RISCVInstrInfo::getOutliningTypeImpl(const MachineModuleInfo &MMI,
       return outliner::InstrType::Illegal;
   }
 
-  // LPADs should not be outlined too
   if (isLPAD(MI))
     return outliner::InstrType::Illegal;
 

llvm/lib/Target/RISCV/RISCVInstrPredicates.td

@@ -148,7 +148,6 @@ def isNonZeroLoadImmediate
                      CheckNot<CheckImmOperand<2, 0>>
                    ]>>>;
 
-// Returns true if this is LPAD (auipc with rd = x0)
 def isLPAD
     : TIIPredicate<"isLPAD",
                    MCReturnStatement<CheckAll<[

llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll

@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple riscv64 -mattr=+experimental-zicfilp < %s | FileCheck %s --check-prefixes=CHECK
-; RUN: llc -mtriple riscv32 -mattr=+experimental-zicfilp < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: llc -mtriple riscv64 -mattr=+experimental-zicfilp < %s | FileCheck %s
+; RUN: llc -mtriple riscv32 -mattr=+experimental-zicfilp < %s | FileCheck %s
 
 define i16 @test1(i16 %x) #0 {
 ; CHECK-LABEL: test1: