Use common register class

Remove target hook. Instead, use common register class to
check if two phis are allowed to reuse the same temp.

Author: jgu222

llvm/include/llvm/CodeGen/TargetInstrInfo.h

@@ -2169,7 +2169,7 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
     return TargetOpcode::COPY;
   }
 
-  /// During PHI elimination lets target to make necessary checks and
+  /// During PHI eleimination lets target to make necessary checks and
   /// insert the copy to the PHI destination register in a target specific
   /// manner.
   virtual MachineInstr *createPHIDestinationCopy(
@@ -2179,7 +2179,7 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
         .addReg(Src);
   }
 
-  /// During PHI elimination lets target to make necessary checks and
+  /// During PHI eleimination lets target to make necessary checks and
   /// insert the copy to the PHI destination register in a target specific
   /// manner.
   virtual MachineInstr *createPHISourceCopy(MachineBasicBlock &MBB,
@@ -2191,17 +2191,6 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
         .addReg(Src, 0, SrcSubReg);
   }
 
-  /// During PHI elimination lets target to decide if two phis can use the
-  /// same register \p Reg when they have the same rhs. Register \p Reg has
-  /// been used for the first phi and \p PHIReg is the DestReg of the second
-  /// Phi. This function is to check if the second phi can reuse \p Reg as
-  /// its temporary register.
-  /// The default is to allow reuse.
-  virtual bool allowPHIReuse(Register Reg, Register PHIReg,
-                             const MachineFunction &MF) const {
-    return true;
-  }
-
   /// Returns a \p outliner::OutlinedFunction struct containing target-specific
   /// information for a set of outlining candidates. Returns std::nullopt if the
   /// candidates are not suitable for outlining. \p MinRepeats is the minimum

llvm/lib/CodeGen/PHIElimination.cpp

@@ -377,10 +377,21 @@ void PHIEliminationImpl::LowerPHINode(MachineBasicBlock &MBB,
     // typically those created by tail duplication. Typically, an identical PHI
     // node can't occur, so avoid hashing/storing such PHIs, which is somewhat
     // expensive.
+
+    // canReuse() checks if two phis of the same rhs have the common sub class
+    // for their lhs's and allow reuse if so. (useful for some GPU targets)
+    auto canReuse = [](Register Reg0, Register Reg1, MachineFunction &MF) {
+      auto &MRI = MF.getRegInfo();
+      auto *RC0 = MRI.getRegClass(Reg0);
+      auto *RC1 = MRI.getRegClass(Reg1);
+      return MF.getSubtarget().getRegisterInfo()->getCommonSubClass(RC0, RC1) !=
+             nullptr;
+    };
+
     Register *Entry = nullptr;
     if (AllEdgesCritical)
       Entry = &LoweredPHIs[MPhi];
-    if (Entry && *Entry && TII->allowPHIReuse(*Entry, DestReg, MF)) {
+    if (Entry && *Entry && canReuse(*Entry, DestReg, MF)) {
       // An identical PHI node was already lowered. Reuse the incoming register.
       IncomingReg = *Entry;
       reusedIncoming = true;

llvm/test/CodeGen/AMDGPU/phi-elimination-reuse-pr163604.mir

@@ -0,0 +1,42 @@
+# RUN: llc -mtriple amdgcn -run-pass phi-node-elimination -o - %s | FileCheck %s
+
+---
+# The test is to make sure that two phis, with the same right-hand-site but different
+# register classes for their left-hand-sites, are not doing phi reuse optimization.
+# Not sure whether this test makes any sense for the AMDGPU target, but it is a valid
+# case for aother GPU target that is not in LLVM trunk yet. Thus, this test uses the
+# ADMGPU target as a proof of concept.
+
+# Because of no reuse for the two phis, there are two temps: CP0 and CP1
+# They are translated to:
+#   phi1 (%1:sreg_32) = CP0
+#   phi2 (%4:vgpr_32) = CP1
+#
+# CHECK-LABEL: check-phi-reuse
+# CHECK-LABEL: bb.1:
+# CHECK: %1:sreg_32 = COPY %[[#CP0:]]
+# CHECK: %[[#CP0]]:sreg_32 = COPY {{.+}}
+# CHECK: %[[#CP1:]]:vgpr_32 = COPY {{.+}}
+# CHECK-LABEL: bb.2:
+# CHECK: %4:vgpr_32 = COPY %[[#CP1]]
+
+
+
+name:            check-phi-reuse
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    %1:sreg_32 = S_MOV_B32 255
+    S_CBRANCH_SCC0 %bb.2, implicit undef $scc
+
+  bb.1:
+    %3:sreg_32 = PHI %4, %bb.1, %1, %bb.0
+    %2:sreg_32 = S_ADD_I32 %3, 1, implicit-def $scc
+    %4:vgpr_32 = COPY %2
+    S_CBRANCH_SCC0 %bb.1, implicit killed $scc
+    S_BRANCH %bb.2
+
+  bb.2:
+    %5:vgpr_32 = PHI %4, %bb.1, %1, %bb.0
+...
+