[X86] LowerFPToIntToFP: return SDValue() for unsigned fp -> int in SSE2

KavinTheG · KavinTheG · commit 1eb12e6a7e9b · 2025-10-15T14:33:24.000-04:00
SSE2 cannot convert unsigned i32 to f32/f64, so return SDValue() in this case. Updated the corresponding X86 fp/int conversion test cases (fp-int-fp-cvt.ll, ftrunc.ll, isint.ll, setoeq.ll) to reflect this change.
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -19963,6 +19963,8 @@ static SDValue lowerFPToIntToFP(SDValue CastToFP, const SDLoc &DL,
     ToFPOpcode = IsUnsigned ? ISD::UINT_TO_FP : ISD::SINT_TO_FP;
   } else {
     // SSE2
+    if (IsUnsigned)
+      return SDValue();
     ToIntOpcode =
         SrcSize != IntSize ? X86ISD::CVTTP2SI : (unsigned)ISD::FP_TO_SINT;
     ToFPOpcode =
diff --git a/llvm/test/CodeGen/X86/fp-int-fp-cvt.ll b/llvm/test/CodeGen/X86/fp-int-fp-cvt.ll
@@ -116,15 +116,24 @@ define float @scvtf32_i64(float %a0) {
 define double @ucvtf64_i32(double %a0) {
 ; SSE-LABEL: ucvtf64_i32:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    cvttpd2dq %xmm0, %xmm0
-; SSE-NEXT:    cvtdq2pd %xmm0, %xmm0
+; SSE-NEXT:    cvttsd2si %xmm0, %rax
+; SSE-NEXT:    movl %eax, %eax
+; SSE-NEXT:    xorps %xmm0, %xmm0
+; SSE-NEXT:    cvtsi2sd %rax, %xmm0
 ; SSE-NEXT:    retq
 ;
-; AVX-LABEL: ucvtf64_i32:
-; AVX:       # %bb.0:
-; AVX-NEXT:    vcvttpd2dq %xmm0, %xmm0
-; AVX-NEXT:    vcvtdq2pd %xmm0, %xmm0
-; AVX-NEXT:    retq
+; AVX2-LABEL: ucvtf64_i32:
+; AVX2:       # %bb.0:
+; AVX2-NEXT:    vcvttsd2si %xmm0, %rax
+; AVX2-NEXT:    movl %eax, %eax
+; AVX2-NEXT:    vcvtsi2sd %rax, %xmm15, %xmm0
+; AVX2-NEXT:    retq
+;
+; AVX512-LABEL: ucvtf64_i32:
+; AVX512:       # %bb.0:
+; AVX512-NEXT:    vcvttsd2usi %xmm0, %eax
+; AVX512-NEXT:    vcvtusi2sd %eax, %xmm15, %xmm0
+; AVX512-NEXT:    retq
   %ii = fptoui double %a0 to i32
   %ff = uitofp i32 %ii to double
   ret double %ff
@@ -186,15 +195,24 @@ define double @ucvtf64_i64(double %a0) {
 define float @ucvtf32_i32(float %a0) {
 ; SSE-LABEL: ucvtf32_i32:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    cvttps2dq %xmm0, %xmm0
-; SSE-NEXT:    cvtdq2ps %xmm0, %xmm0
+; SSE-NEXT:    cvttss2si %xmm0, %rax
+; SSE-NEXT:    movl %eax, %eax
+; SSE-NEXT:    xorps %xmm0, %xmm0
+; SSE-NEXT:    cvtsi2ss %rax, %xmm0
 ; SSE-NEXT:    retq
 ;
-; AVX-LABEL: ucvtf32_i32:
-; AVX:       # %bb.0:
-; AVX-NEXT:    vcvttps2dq %xmm0, %xmm0
-; AVX-NEXT:    vcvtdq2ps %xmm0, %xmm0
-; AVX-NEXT:    retq
+; AVX2-LABEL: ucvtf32_i32:
+; AVX2:       # %bb.0:
+; AVX2-NEXT:    vcvttss2si %xmm0, %rax
+; AVX2-NEXT:    movl %eax, %eax
+; AVX2-NEXT:    vcvtsi2ss %rax, %xmm15, %xmm0
+; AVX2-NEXT:    retq
+;
+; AVX512-LABEL: ucvtf32_i32:
+; AVX512:       # %bb.0:
+; AVX512-NEXT:    vcvttss2usi %xmm0, %eax
+; AVX512-NEXT:    vcvtusi2ss %eax, %xmm15, %xmm0
+; AVX512-NEXT:    retq
   %ii = fptoui float %a0 to i32
   %ff = uitofp i32 %ii to float
   ret float %ff
@@ -265,5 +283,3 @@ define float @ucvtf32_i64(float %a0) {
   %ff = uitofp i64 %ii to float
   ret float %ff
 }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; AVX512: {{.*}}
diff --git a/llvm/test/CodeGen/X86/ftrunc.ll b/llvm/test/CodeGen/X86/ftrunc.ll
@@ -10,8 +10,10 @@ declare i64 @llvm.fptosi.sat.i64.f64(double)
 define float @trunc_unsigned_f32(float %x) #0 {
 ; SSE2-LABEL: trunc_unsigned_f32:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    cvttps2dq %xmm0, %xmm0
-; SSE2-NEXT:    cvtdq2ps %xmm0, %xmm0
+; SSE2-NEXT:    cvttss2si %xmm0, %rax
+; SSE2-NEXT:    movl %eax, %eax
+; SSE2-NEXT:    xorps %xmm0, %xmm0
+; SSE2-NEXT:    cvtsi2ss %rax, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; SSE41-LABEL: trunc_unsigned_f32:
diff --git a/llvm/test/CodeGen/X86/isint.ll b/llvm/test/CodeGen/X86/isint.ll
@@ -207,8 +207,9 @@ define i32 @isuint_return(double %d) nounwind {
 ;
 ; X86-LABEL: isuint_return:
 ; X86:       # %bb.0:
-; X86-NEXT:    cvttpd2dq %xmm0, %xmm1
-; X86-NEXT:    cvtdq2pd %xmm1, %xmm1
+; X86-NEXT:    cvttsd2si %xmm0, %rax
+; X86-NEXT:    movl %eax, %eax
+; X86-NEXT:    cvtsi2sd %rax, %xmm1
 ; X86-NEXT:    cmpeqsd %xmm0, %xmm1
 ; X86-NEXT:    movq %xmm1, %rax
 ; X86-NEXT:    andl $1, %eax
@@ -218,17 +219,26 @@ define i32 @isuint_return(double %d) nounwind {
 ; SSE2-LABEL: isuint_return:
 ; SSE2:       # %bb.0:
 ; SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE2-NEXT:    cvttpd2dq %xmm0, %xmm1
-; SSE2-NEXT:    cvtdq2pd %xmm1, %xmm1
+; SSE2-NEXT:    cvttsd2si %xmm0, %eax
+; SSE2-NEXT:    movl %eax, %ecx
+; SSE2-NEXT:    sarl $31, %ecx
+; SSE2-NEXT:    movapd %xmm0, %xmm1
+; SSE2-NEXT:    subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; SSE2-NEXT:    cvttsd2si %xmm1, %edx
+; SSE2-NEXT:    andl %ecx, %edx
+; SSE2-NEXT:    orl %eax, %edx
+; SSE2-NEXT:    movd %edx, %xmm1
+; SSE2-NEXT:    por {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; SSE2-NEXT:    subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
 ; SSE2-NEXT:    cmpeqsd %xmm0, %xmm1
 ; SSE2-NEXT:    movd %xmm1, %eax
 ; SSE2-NEXT:    andl $1, %eax
 ; SSE2-NEXT:    retl
 ;
 ; AVX512VL-LABEL: isuint_return:
 ; AVX512VL:       # %bb.0:
-; AVX512VL-NEXT:    vcvttpd2dq %xmm0, %xmm1
-; AVX512VL-NEXT:    vcvtdq2pd %xmm1, %xmm1
+; AVX512VL-NEXT:    vcvttsd2usi %xmm0, %eax
+; AVX512VL-NEXT:    vcvtusi2sd %eax, %xmm15, %xmm1
 ; AVX512VL-NEXT:    vcmpeqsd %xmm1, %xmm0, %k0
 ; AVX512VL-NEXT:    kmovw %k0, %eax
 ; AVX512VL-NEXT:    retq
diff --git a/llvm/test/CodeGen/X86/setoeq.ll b/llvm/test/CodeGen/X86/setoeq.ll
@@ -47,8 +47,17 @@ define zeroext i8 @oeq_f64_u32(double %x) nounwind readnone {
 ; SSE-LABEL: oeq_f64_u32:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE-NEXT:    cvttpd2dq %xmm0, %xmm1
-; SSE-NEXT:    cvtdq2pd %xmm1, %xmm1
+; SSE-NEXT:    cvttsd2si %xmm0, %eax
+; SSE-NEXT:    movl %eax, %ecx
+; SSE-NEXT:    sarl $31, %ecx
+; SSE-NEXT:    movapd %xmm0, %xmm1
+; SSE-NEXT:    subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; SSE-NEXT:    cvttsd2si %xmm1, %edx
+; SSE-NEXT:    andl %ecx, %edx
+; SSE-NEXT:    orl %eax, %edx
+; SSE-NEXT:    movd %edx, %xmm1
+; SSE-NEXT:    por {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; SSE-NEXT:    subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
 ; SSE-NEXT:    cmpeqsd %xmm0, %xmm1
 ; SSE-NEXT:    movd %xmm1, %eax
 ; SSE-NEXT:    andl $1, %eax
@@ -58,8 +67,16 @@ define zeroext i8 @oeq_f64_u32(double %x) nounwind readnone {
 ; AVX-LABEL: oeq_f64_u32:
 ; AVX:       # %bb.0: # %entry
 ; AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX-NEXT:    vcvttpd2dq %xmm0, %xmm1
-; AVX-NEXT:    vcvtdq2pd %xmm1, %xmm1
+; AVX-NEXT:    vcvttsd2si %xmm0, %eax
+; AVX-NEXT:    movl %eax, %ecx
+; AVX-NEXT:    sarl $31, %ecx
+; AVX-NEXT:    vsubsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm1
+; AVX-NEXT:    vcvttsd2si %xmm1, %edx
+; AVX-NEXT:    andl %ecx, %edx
+; AVX-NEXT:    orl %eax, %edx
+; AVX-NEXT:    vmovd %edx, %xmm1
+; AVX-NEXT:    vpor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
+; AVX-NEXT:    vsubsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
 ; AVX-NEXT:    vcmpeqsd %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    vmovd %xmm0, %eax
 ; AVX-NEXT:    andl $1, %eax
@@ -69,8 +86,8 @@ define zeroext i8 @oeq_f64_u32(double %x) nounwind readnone {
 ; AVX512-LABEL: oeq_f64_u32:
 ; AVX512:       # %bb.0: # %entry
 ; AVX512-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX512-NEXT:    vcvttpd2dq %xmm0, %xmm1
-; AVX512-NEXT:    vcvtdq2pd %xmm1, %xmm1
+; AVX512-NEXT:    vcvttsd2usi %xmm0, %eax
+; AVX512-NEXT:    vcvtusi2sd %eax, %xmm7, %xmm1
 ; AVX512-NEXT:    vcmpeqsd %xmm0, %xmm1, %k0
 ; AVX512-NEXT:    kmovd %k0, %eax
 ; AVX512-NEXT:    # kill: def $al killed $al killed $eax
@@ -294,8 +311,17 @@ define zeroext i8 @une_f64_u32(double %x) nounwind readnone {
 ; SSE-LABEL: une_f64_u32:
 ; SSE:       # %bb.0: # %entry
 ; SSE-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE-NEXT:    cvttpd2dq %xmm0, %xmm1
-; SSE-NEXT:    cvtdq2pd %xmm1, %xmm1
+; SSE-NEXT:    cvttsd2si %xmm0, %eax
+; SSE-NEXT:    movl %eax, %ecx
+; SSE-NEXT:    sarl $31, %ecx
+; SSE-NEXT:    movapd %xmm0, %xmm1
+; SSE-NEXT:    subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; SSE-NEXT:    cvttsd2si %xmm1, %edx
+; SSE-NEXT:    andl %ecx, %edx
+; SSE-NEXT:    orl %eax, %edx
+; SSE-NEXT:    movd %edx, %xmm1
+; SSE-NEXT:    por {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
+; SSE-NEXT:    subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
 ; SSE-NEXT:    cmpneqsd %xmm0, %xmm1
 ; SSE-NEXT:    movd %xmm1, %eax
 ; SSE-NEXT:    andl $1, %eax
@@ -305,8 +331,16 @@ define zeroext i8 @une_f64_u32(double %x) nounwind readnone {
 ; AVX-LABEL: une_f64_u32:
 ; AVX:       # %bb.0: # %entry
 ; AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX-NEXT:    vcvttpd2dq %xmm0, %xmm1
-; AVX-NEXT:    vcvtdq2pd %xmm1, %xmm1
+; AVX-NEXT:    vcvttsd2si %xmm0, %eax
+; AVX-NEXT:    movl %eax, %ecx
+; AVX-NEXT:    sarl $31, %ecx
+; AVX-NEXT:    vsubsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm1
+; AVX-NEXT:    vcvttsd2si %xmm1, %edx
+; AVX-NEXT:    andl %ecx, %edx
+; AVX-NEXT:    orl %eax, %edx
+; AVX-NEXT:    vmovd %edx, %xmm1
+; AVX-NEXT:    vpor {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
+; AVX-NEXT:    vsubsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
 ; AVX-NEXT:    vcmpneqsd %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    vmovd %xmm0, %eax
 ; AVX-NEXT:    andl $1, %eax
@@ -316,8 +350,8 @@ define zeroext i8 @une_f64_u32(double %x) nounwind readnone {
 ; AVX512-LABEL: une_f64_u32:
 ; AVX512:       # %bb.0: # %entry
 ; AVX512-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX512-NEXT:    vcvttpd2dq %xmm0, %xmm1
-; AVX512-NEXT:    vcvtdq2pd %xmm1, %xmm1
+; AVX512-NEXT:    vcvttsd2usi %xmm0, %eax
+; AVX512-NEXT:    vcvtusi2sd %eax, %xmm7, %xmm1
 ; AVX512-NEXT:    vcmpneqsd %xmm0, %xmm1, %k0
 ; AVX512-NEXT:    kmovd %k0, %eax
 ; AVX512-NEXT:    # kill: def $al killed $al killed $eax
