Feedback, correct tests

Author: JanekvO

llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir

@@ -12,9 +12,6 @@
 # CHECK:         flat_store_dwordx3 v[2:3], v[4:6]
 # CHECK:         s_endpgm
 
---- |
-  define void @misaligned_regsequence() { ret void }
-...
 ---
 name: misaligned_regsequence
 tracksRegLiveness: true

llvm/test/CodeGen/AMDGPU/siloadstoreopt-misaligned-regsequence.ll

@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck %s
+
+define amdgpu_kernel void @foo(ptr %0) {
+; CHECK-LABEL: foo:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; CHECK-NEXT:    v_mov_b32_e32 v2, 0
+; CHECK-NEXT:    v_mov_b32_e32 v3, v2
+; CHECK-NEXT:    v_mov_b32_e32 v4, v3
+; CHECK-NEXT:    v_mov_b32_e32 v3, v2
+; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b64_e32 v[0:1], s[0:1]
+; CHECK-NEXT:    flat_store_dwordx3 v[0:1], v[2:4]
+; CHECK-NEXT:    s_endpgm
+entry:
+  %1 = getelementptr i8, ptr %0, i64 4
+  store i32 0, ptr %0, align 4
+  store i64 0, ptr %1, align 4
+  ret void
+}

llvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir

@@ -93,12 +93,3 @@ body: |
   bb.0:
     $vgpr0_vgpr1 = V_MOV_B64_PSEUDO 4575657222473777152, implicit $exec
 ...
-
-# GCN-LABEL: name: v_mov_b64_misalign
-# GCN: $vgpr5 = V_MOV_B32_e32 0, implicit $exec, implicit-def $vgpr5_vgpr6
-# GCN: $vgpr6 = V_MOV_B32_e32 0, implicit $exec, implicit-def $vgpr5_vgpr6
-name: v_mov_b64_misalign
-body: |
-  bb.0:
-    $vgpr5_vgpr6 = V_MOV_B64_PSEUDO 0, implicit $exec
-...