@@ -4225,9 +4225,12 @@ void CombinerHelper::applyExtractVecEltBuildVec(MachineInstr &MI,
42254225}
42264226
42274227bool CombinerHelper::matchCombineExtractToShuffle (
4228- MachineInstr &MI, SmallVectorImpl<std::pair< Register, int >> &VecIndexPair ,
4228+ MachineInstr &MI, SmallVectorImpl<Register> &Ops ,
42294229 std::pair<Register, Register> &VectorRegisters) {
42304230 const GBuildVector *Build = cast<GBuildVector>(&MI);
4231+ const unsigned SrcNumElts =
4232+ MRI.getType (MI.getOperand (0 ).getReg ()).getNumElements ();
4233+
42314234 // This combine tries to find all the build vectors whose source elements
42324235 // all originate from a G_EXTRACT_VECTOR_ELT from one or two donor vectors.
42334236 // One example where this may happen is for AI chips where there are a lot
@@ -4245,24 +4248,29 @@ bool CombinerHelper::matchCombineExtractToShuffle(
42454248 // replace with:
42464249 // %vector = G_SHUFFLE_VECTOR %donor1, %donor2, shufflemask(0, 1, 2, 3)
42474250 SmallSetVector<Register, 2 > RegisterVector;
4251+ SmallVector<int , 32 > VectorMask;
42484252 const unsigned NumElements = Build->getNumSources ();
42494253 for (unsigned Index = 0 ; Index < NumElements; Index++) {
42504254 Register SrcReg = peekThroughBitcast (Build->getSourceReg (Index), MRI);
42514255 auto *ExtractInstr = getOpcodeDef<GExtractVectorElement>(SrcReg, MRI);
42524256 if (!ExtractInstr)
42534257 return false ;
42544258
4259+ RegisterVector.insert (ExtractInstr->getVectorReg ());
4260+
42554261 // For shufflemasks we need to know exactly what index to place each element
42564262 // so if it this build vector doesn't use exclusively constants than we
42574263 // can't replace with a shufflevector
42584264 auto Cst = getIConstantVRegVal (ExtractInstr->getIndexReg (), MRI);
42594265 if (!Cst)
42604266 return false ;
4267+
42614268 unsigned Idx = Cst->getZExtValue ();
4269+ if (ExtractInstr->getVectorReg () != RegisterVector.front ()) {
4270+ Idx += SrcNumElts;
4271+ }
42624272
4263- Register VectorReg = ExtractInstr->getVectorReg ();
4264- RegisterVector.insert (VectorReg);
4265- VecIndexPair.emplace_back (std::make_pair (VectorReg, Idx));
4273+ VectorMask.emplace_back (Idx);
42664274 }
42674275
42684276 // Create a pair so that we don't need to look for them later. This code is
@@ -4273,44 +4281,17 @@ bool CombinerHelper::matchCombineExtractToShuffle(
42734281 std::make_pair (RegisterVector.front (), RegisterVector.back ());
42744282
42754283 // We check that they're the same type before running. We can also grow the
4276- // smaller one to the target size, but there isn't an elegant way to do that
4277- // until we have a good lowering for G_EXTRACT_SUBVECTOR.
4284+ // smaller one tro the target size, but there isn't an elegant way to do that
4285+ // until we have a good lowerng for G_EXTRACT_SUBVECTOR.
4286+ // Apparently if they are the same, they don't necessary have the same type?
42784287 if (MRI.getType (VectorRegisters.first ) != MRI.getType (VectorRegisters.second ))
42794288 return false ;
42804289
4281- return RegisterVector.size () <= 2 ;
4282- }
4283-
4284- void CombinerHelper::applyCombineExtractToShuffle (
4285- MachineInstr &MI, SmallVectorImpl<std::pair<Register, int >> &MatchInfo,
4286- std::pair<Register, Register> &VectorRegisters) {
4287- assert (MI.getOpcode () == TargetOpcode::G_BUILD_VECTOR);
4288-
4289- const Register FirstRegister = VectorRegisters.first ;
4290- const LLT FirstRegisterType = MRI.getType (FirstRegister);
4291- const unsigned VectorSize = FirstRegisterType.getNumElements ();
4292- SmallVector<int , 32 > ShuffleMask;
4293- for (auto &Pair : MatchInfo) {
4294- const Register VectorReg = Pair.first ;
4295- int Idx = Pair.second ;
4296-
4297- if (VectorReg != VectorRegisters.first ) {
4298- Idx += VectorSize;
4299- }
4300- ShuffleMask.emplace_back (Idx);
4301- }
4302-
4303- // We could reuse the same vector register and shuffle them both together
4304- // but it is nicer for later optimizations to explicitly make it undef.
4305- const GBuildVector *BuildVector = cast<GBuildVector>(&MI);
4306- Register SecondRegister = VectorRegisters.second ;
4307- if (FirstRegister == SecondRegister) {
4308- SecondRegister = Builder.buildUndef (FirstRegisterType).getReg (0 );
4309- }
4290+ if (RegisterVector.size () > 2 )
4291+ return false ;
43104292
4311- Builder.buildShuffleVector (BuildVector->getOperand (0 ), FirstRegister,
4312- SecondRegister, ShuffleMask);
4313- MI.eraseFromParent ();
4293+ return analysePatternVectorMask (MI, Ops, MI.getOperand (0 ).getReg (),
4294+ VectorRegisters, VectorMask);
43144295}
43154296
43164297bool CombinerHelper::matchExtractAllEltsFromBuildVector (
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