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[ARM] Reject fixed-point VCVT with different registers (#126232)
These instructions only have one register field in their encoding, so both registers in the assembly must be the same. Previously, we were accepting these instructions, but ignoring the second register operand. Fixes #126227
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5 files changed

+146
-64
lines changed

‎llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8652,6 +8652,37 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
86528652
"coprocessor must be configured as GCP");
86538653
break;
86548654
}
8655+
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case ARM::VTOSHH:
8657+
case ARM::VTOUHH:
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case ARM::VTOSLH:
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case ARM::VTOULH:
8660+
case ARM::VTOSHS:
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case ARM::VTOUHS:
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case ARM::VTOSLS:
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case ARM::VTOULS:
8664+
case ARM::VTOSHD:
8665+
case ARM::VTOUHD:
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case ARM::VTOSLD:
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case ARM::VTOULD:
8668+
case ARM::VSHTOH:
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case ARM::VUHTOH:
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case ARM::VSLTOH:
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case ARM::VULTOH:
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case ARM::VSHTOS:
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case ARM::VUHTOS:
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case ARM::VSLTOS:
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case ARM::VULTOS:
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case ARM::VSHTOD:
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case ARM::VUHTOD:
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case ARM::VSLTOD:
8679+
case ARM::VULTOD: {
8680+
if (Operands[MnemonicOpsEndInd]->getReg() !=
8681+
Operands[MnemonicOpsEndInd + 1]->getReg())
8682+
return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
8683+
"source and destination registers must be the same");
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break;
8685+
}
86558686
}
86568687

86578688
return false;

‎llvm/test/MC/ARM/vcvt-fixed-point-errors.s‎

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,51 @@
1+
// RUN: not llvm-mc -triple=armv8a-none-eabi -mattr=+fullfp16 < %s 2>&1 | FileCheck %s
2+
3+
vcvt.u16.f16 s0, s1, #1
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// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
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vcvt.s16.f16 s0, s1, #1
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// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
7+
vcvt.u32.f16 s0, s1, #1
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// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
9+
vcvt.s32.f16 s0, s1, #1
10+
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
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vcvt.u16.f32 s0, s1, #1
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// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
13+
vcvt.s16.f32 s0, s1, #1
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// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
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vcvt.u32.f32 s0, s1, #1
16+
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
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vcvt.s32.f32 s0, s1, #1
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// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
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vcvt.u16.f64 d0, d1, #1
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// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
21+
vcvt.s16.f64 d0, d1, #1
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// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
23+
vcvt.u32.f64 d0, d1, #1
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// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
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vcvt.s32.f64 d0, d1, #1
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// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
27+
vcvt.f16.u16 s0, s1, #1
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// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
29+
vcvt.f16.s16 s0, s1, #1
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// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
31+
vcvt.f16.u32 s0, s1, #1
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// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
33+
vcvt.f16.s32 s0, s1, #1
34+
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
35+
vcvt.f32.u16 s0, s1, #1
36+
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
37+
vcvt.f32.s16 s0, s1, #1
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// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
39+
vcvt.f32.u32 s0, s1, #1
40+
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
41+
vcvt.f32.s32 s0, s1, #1
42+
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
43+
vcvt.f64.u16 d0, d1, #1
44+
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
45+
vcvt.f64.s16 d0, d1, #1
46+
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
47+
vcvt.f64.u32 d0, d1, #1
48+
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
49+
vcvt.f64.s32 d0, d1, #1
50+
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
51+

‎llvm/test/tools/llvm-mca/ARM/m55-fp.s‎

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -21,30 +21,30 @@ vcmpe.f32 s1, #0.0
2121
vcmpe.f64 d1, #0.0
2222
vcvt.f32.f64 s1, d2
2323
vcvt.f64.f32 d1, s1
24-
vcvt.f16.u16 s1, s2, #8
25-
vcvt.f16.s16 s1, s2, #8
26-
vcvt.f16.u32 s1, s2, #8
27-
vcvt.f16.s32 s1, s2, #8
28-
vcvt.u16.f16 s1, s2, #8
29-
vcvt.s16.f16 s1, s2, #8
30-
vcvt.u32.f16 s1, s2, #8
31-
vcvt.s32.f16 s1, s2, #8
32-
vcvt.f32.u16 s1, s2, #8
33-
vcvt.f32.s16 s1, s2, #8
34-
vcvt.f32.u32 s1, s2, #8
35-
vcvt.f32.s32 s1, s2, #8
36-
vcvt.u16.f32 s1, s2, #8
37-
vcvt.s16.f32 s1, s2, #8
38-
vcvt.u32.f32 s1, s2, #8
39-
vcvt.s32.f32 s1, s2, #8
40-
vcvt.f64.u16 d1, d2, #8
41-
vcvt.f64.s16 d1, d2, #8
42-
vcvt.f64.u32 d1, d2, #8
43-
vcvt.f64.s32 d1, d2, #8
44-
vcvt.u16.f64 d1, d2, #8
45-
vcvt.s16.f64 d1, d2, #8
46-
vcvt.u32.f64 d1, d2, #8
47-
vcvt.s32.f64 d1, d2, #8
24+
vcvt.f16.u16 s1, s1, #8
25+
vcvt.f16.s16 s1, s1, #8
26+
vcvt.f16.u32 s1, s1, #8
27+
vcvt.f16.s32 s1, s1, #8
28+
vcvt.u16.f16 s1, s1, #8
29+
vcvt.s16.f16 s1, s1, #8
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vcvt.u32.f16 s1, s1, #8
31+
vcvt.s32.f16 s1, s1, #8
32+
vcvt.f32.u16 s1, s1, #8
33+
vcvt.f32.s16 s1, s1, #8
34+
vcvt.f32.u32 s1, s1, #8
35+
vcvt.f32.s32 s1, s1, #8
36+
vcvt.u16.f32 s1, s1, #8
37+
vcvt.s16.f32 s1, s1, #8
38+
vcvt.u32.f32 s1, s1, #8
39+
vcvt.s32.f32 s1, s1, #8
40+
vcvt.f64.u16 d1, d1, #8
41+
vcvt.f64.s16 d1, d1, #8
42+
vcvt.f64.u32 d1, d1, #8
43+
vcvt.f64.s32 d1, d1, #8
44+
vcvt.u16.f64 d1, d1, #8
45+
vcvt.s16.f64 d1, d1, #8
46+
vcvt.u32.f64 d1, d1, #8
47+
vcvt.s32.f64 d1, d1, #8
4848
vcvt.u32.f16 s1, s2
4949
vcvt.s32.f16 s1, s2
5050
vcvt.u32.f32 s1, s2

‎llvm/test/tools/llvm-mca/ARM/m7-fp.s‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -9,22 +9,22 @@ vcmp.f32 s1, s2
99
vcmp.f64 d1, d2
1010
vcvt.f32.f64 s1, d2
1111
vcvt.f64.f32 d1, s1
12-
vcvt.f32.u16 s1, s2, #8
13-
vcvt.f32.s16 s1, s2, #8
14-
vcvt.f32.u32 s1, s2, #8
15-
vcvt.f32.s32 s1, s2, #8
16-
vcvt.u16.f32 s1, s2, #8
17-
vcvt.s16.f32 s1, s2, #8
18-
vcvt.u32.f32 s1, s2, #8
19-
vcvt.s32.f32 s1, s2, #8
20-
vcvt.f64.u16 d1, d2, #8
21-
vcvt.f64.s16 d1, d2, #8
22-
vcvt.f64.u32 d1, d2, #8
23-
vcvt.f64.s32 d1, d2, #8
24-
vcvt.u16.f64 d1, d2, #8
25-
vcvt.s16.f64 d1, d2, #8
26-
vcvt.u32.f64 d1, d2, #8
27-
vcvt.s32.f64 d1, d2, #8
12+
vcvt.f32.u16 s1, s1, #8
13+
vcvt.f32.s16 s1, s1, #8
14+
vcvt.f32.u32 s1, s1, #8
15+
vcvt.f32.s32 s1, s1, #8
16+
vcvt.u16.f32 s1, s1, #8
17+
vcvt.s16.f32 s1, s1, #8
18+
vcvt.u32.f32 s1, s1, #8
19+
vcvt.s32.f32 s1, s1, #8
20+
vcvt.f64.u16 d1, d1, #8
21+
vcvt.f64.s16 d1, d1, #8
22+
vcvt.f64.u32 d1, d1, #8
23+
vcvt.f64.s32 d1, d1, #8
24+
vcvt.u16.f64 d1, d1, #8
25+
vcvt.s16.f64 d1, d1, #8
26+
vcvt.u32.f64 d1, d1, #8
27+
vcvt.s32.f64 d1, d1, #8
2828
vcvt.u32.f32 s1, s2
2929
vcvt.s32.f32 s1, s2
3030
vcvt.u32.f64 s1, d2

‎llvm/test/tools/llvm-mca/ARM/m85-fp.s‎

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -21,30 +21,30 @@ vcmpe.f32 s1, #0.0
2121
vcmpe.f64 d1, #0.0
2222
vcvt.f32.f64 s1, d2
2323
vcvt.f64.f32 d1, s1
24-
vcvt.f16.u16 s1, s2, #8
25-
vcvt.f16.s16 s1, s2, #8
26-
vcvt.f16.u32 s1, s2, #8
27-
vcvt.f16.s32 s1, s2, #8
28-
vcvt.u16.f16 s1, s2, #8
29-
vcvt.s16.f16 s1, s2, #8
30-
vcvt.u32.f16 s1, s2, #8
31-
vcvt.s32.f16 s1, s2, #8
32-
vcvt.f32.u16 s1, s2, #8
33-
vcvt.f32.s16 s1, s2, #8
34-
vcvt.f32.u32 s1, s2, #8
35-
vcvt.f32.s32 s1, s2, #8
36-
vcvt.u16.f32 s1, s2, #8
37-
vcvt.s16.f32 s1, s2, #8
38-
vcvt.u32.f32 s1, s2, #8
39-
vcvt.s32.f32 s1, s2, #8
40-
vcvt.f64.u16 d1, d2, #8
41-
vcvt.f64.s16 d1, d2, #8
42-
vcvt.f64.u32 d1, d2, #8
43-
vcvt.f64.s32 d1, d2, #8
44-
vcvt.u16.f64 d1, d2, #8
45-
vcvt.s16.f64 d1, d2, #8
46-
vcvt.u32.f64 d1, d2, #8
47-
vcvt.s32.f64 d1, d2, #8
24+
vcvt.f16.u16 s1, s1, #8
25+
vcvt.f16.s16 s1, s1, #8
26+
vcvt.f16.u32 s1, s1, #8
27+
vcvt.f16.s32 s1, s1, #8
28+
vcvt.u16.f16 s1, s1, #8
29+
vcvt.s16.f16 s1, s1, #8
30+
vcvt.u32.f16 s1, s1, #8
31+
vcvt.s32.f16 s1, s1, #8
32+
vcvt.f32.u16 s1, s1, #8
33+
vcvt.f32.s16 s1, s1, #8
34+
vcvt.f32.u32 s1, s1, #8
35+
vcvt.f32.s32 s1, s1, #8
36+
vcvt.u16.f32 s1, s1, #8
37+
vcvt.s16.f32 s1, s1, #8
38+
vcvt.u32.f32 s1, s1, #8
39+
vcvt.s32.f32 s1, s1, #8
40+
vcvt.f64.u16 d1, d1, #8
41+
vcvt.f64.s16 d1, d1, #8
42+
vcvt.f64.u32 d1, d1, #8
43+
vcvt.f64.s32 d1, d1, #8
44+
vcvt.u16.f64 d1, d1, #8
45+
vcvt.s16.f64 d1, d1, #8
46+
vcvt.u32.f64 d1, d1, #8
47+
vcvt.s32.f64 d1, d1, #8
4848
vcvt.u32.f16 s1, s2
4949
vcvt.s32.f16 s1, s2
5050
vcvt.u32.f32 s1, s2

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