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[DAG] Fold (umin (sub a b) a) -> (usubo a b); (select usubo.1 a usubo.0) (#161651)
Fixes #161036.
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‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6219,6 +6219,25 @@ SDValue DAGCombiner::visitIMINMAX(SDNode *N) {
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SDLoc(N), VT, N0, N1))
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return SD;
62216221

6222+
if (TLI.isOperationLegalOrCustom(ISD::USUBO, VT) &&
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!TLI.isOperationLegalOrCustom(ISD::UMIN, VT)) {
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SDValue B;
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// (umin (sub a, b), a) -> (usubo a, b); (select usubo.1, a, usubo.0)
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if (sd_match(N0, m_Sub(m_Specific(N1), m_Value(B)))) {
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SDVTList VTs = DAG.getVTList(VT, getSetCCResultType(VT));
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SDValue USO = DAG.getNode(ISD::USUBO, DL, VTs, N1, B);
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return DAG.getSelect(DL, VT, USO.getValue(1), N1, USO.getValue(0));
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}
6232+
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// (umin a, (sub a, b)) -> (usubo a, b); (select usubo.1, a, usubo.0)
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if (sd_match(N1, m_Sub(m_Specific(N0), m_Value(B)))) {
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SDVTList VTs = DAG.getVTList(VT, getSetCCResultType(VT));
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SDValue USO = DAG.getNode(ISD::USUBO, DL, VTs, N0, B);
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return DAG.getSelect(DL, VT, USO.getValue(1), N0, USO.getValue(0));
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}
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}
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62226241
// Simplify the operands using demanded-bits information.
62236242
if (SimplifyDemandedBits(SDValue(N, 0)))
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return SDValue(N, 0);

‎llvm/test/CodeGen/AArch64/umin-sub-to-usubo-select-combine.ll‎

Lines changed: 151 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,151 @@
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; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
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; GitHub issue #161036
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; Positive test : umin(sub(a,b),a) with scalar types should be folded
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define i64 @underflow_compare_fold_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: underflow_compare_fold_i64
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; CHECK-LABEL: %bb.0:
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; CHECK-NEXT: subs x8, x0, x1
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; CHECK-NEXT: csel x0, x0, x8, lo
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; CHECK-NEXT: ret
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%sub = sub i64 %a, %b
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%cond = tail call i64 @llvm.umin.i64(i64 %sub, i64 %a)
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ret i64 %cond
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}
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; Positive test : umin(a,sub(a,b)) with scalar types should be folded
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define i64 @underflow_compare_fold_i64_commute(i64 %a, i64 %b) {
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; CHECK-LABEL: underflow_compare_fold_i64_commute
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; CHECK-LABEL: %bb.0:
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; CHECK-NEXT: subs x8, x0, x1
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; CHECK-NEXT: csel x0, x0, x8, lo
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; CHECK-NEXT: ret
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%sub = sub i64 %a, %b
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%cond = tail call i64 @llvm.umin.i64(i64 %a, i64 %sub)
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ret i64 %cond
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}
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; Positive test : multi-use is OK since the sub instruction still runs once
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define i64 @underflow_compare_fold_i64_multi_use(i64 %a, i64 %b, ptr addrspace(1) %ptr) {
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; CHECK-LABEL: underflow_compare_fold_i64_multi_use
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; CHECK-LABEL: %bb.0:
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; CHECK-NEXT: subs x8, x0, x1
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; CHECK-NEXT: csel x0, x0, x8, lo
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; CHECK-NEXT: str x8, [x2]
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; CHECK-NEXT: ret
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%sub = sub i64 %a, %b
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store i64 %sub, ptr addrspace(1) %ptr
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%cond = call i64 @llvm.umin.i64(i64 %sub, i64 %a)
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ret i64 %cond
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}
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; Positive test : i32
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define i32 @underflow_compare_fold_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: underflow_compare_fold_i32
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; CHECK-LABEL: %bb.0:
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; CHECK-NEXT: subs w8, w0, w1
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; CHECK-NEXT: csel w0, w0, w8, lo
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; CHECK-NEXT: ret
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%sub = sub i32 %a, %b
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%cond = tail call i32 @llvm.umin.i32(i32 %sub, i32 %a)
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ret i32 %cond
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}
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; Positive test : i32
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define i32 @underflow_compare_fold_i32_commute(i32 %a, i32 %b) {
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; CHECK-LABEL: underflow_compare_fold_i32_commute
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; CHECK-LABEL: %bb.0:
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; CHECK-NEXT: subs w8, w0, w1
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; CHECK-NEXT: csel w0, w0, w8, lo
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; CHECK-NEXT: ret
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%sub = sub i32 %a, %b
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%cond = tail call i32 @llvm.umin.i32(i32 %a, i32 %sub)
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ret i32 %cond
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}
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; Positive test : i32
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define i32 @underflow_compare_fold_i32_multi_use(i32 %a, i32 %b, ptr addrspace(1) %ptr) {
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; CHECK-LABEL: underflow_compare_fold_i32_multi_use
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; CHECK-LABEL: %bb.0:
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; CHECK-NEXT: subs w8, w0, w1
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; CHECK-NEXT: csel w0, w0, w8, lo
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; CHECK-NEXT: str w8, [x2]
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; CHECK-NEXT: ret
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%sub = sub i32 %a, %b
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store i32 %sub, ptr addrspace(1) %ptr
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%cond = call i32 @llvm.umin.i32(i32 %sub, i32 %a)
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ret i32 %cond
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}
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; Negative test : i16
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define i16 @underflow_compare_fold_i16(i16 %a, i16 %b) {
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; CHECK-LABEL: underflow_compare_fold_i16
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; CHECK-LABEL: %bb.0:
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; CHECK-LABEL: sub w8, w0, w1
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; CHECK-LABEL: and w9, w0, #0xffff
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; CHECK-LABEL: and w8, w8, #0xffff
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; CHECK-LABEL: cmp w8, w9
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; CHECK-LABEL: csel w0, w8, w9, lo
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; CHECK-LABEL: ret
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%sub = sub i16 %a, %b
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%cond = tail call i16 @llvm.umin.i16(i16 %sub, i16 %a)
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ret i16 %cond
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}
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; Negative test : i16
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define i16 @underflow_compare_fold_i16_commute(i16 %a, i16 %b) {
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; CHECK-LABEL: underflow_compare_fold_i16_commute
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; CHECK-LABEL: %bb.0:
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; CHECK-LABEL: sub w8, w0, w1
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; CHECK-LABEL: and w9, w0, #0xffff
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; CHECK-LABEL: and w8, w8, #0xffff
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; CHECK-LABEL: cmp w9, w8
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; CHECK-LABEL: csel w0, w9, w8, lo
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; CHECK-LABEL: ret
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%sub = sub i16 %a, %b
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%cond = tail call i16 @llvm.umin.i16(i16 %a, i16 %sub)
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ret i16 %cond
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}
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; Negative test : i16
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define i16 @underflow_compare_fold_i16_multi_use(i16 %a, i16 %b, ptr addrspace(1) %ptr) {
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; CHECK-LABEL: underflow_compare_fold_i16_multi_use
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; CHECK-LABEL: %bb.0:
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; CHECK-LABEL: sub w8, w0, w1
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; CHECK-LABEL: and w9, w0, #0xffff
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; CHECK-LABEL: and w10, w8, #0xffff
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; CHECK-LABEL: strh w8, [x2]
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; CHECK-LABEL: cmp w10, w9
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; CHECK-LABEL: csel w0, w10, w9, lo
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; CHECK-LABEL: ret
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%sub = sub i16 %a, %b
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store i16 %sub, ptr addrspace(1) %ptr
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%cond = call i16 @llvm.umin.i16(i16 %sub, i16 %a)
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ret i16 %cond
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}
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; Negative test, vector types : umin(sub(a,b),a) but with vectors
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define <16 x i8> @underflow_compare_dontfold_vectors(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: underflow_compare_dontfold_vectors
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; CHECK-LABEL: %bb.0
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; CHECK-NEXT: sub v1.16b, v0.16b, v1.16b
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; CHECK-NEXT: umin v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: ret
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%sub = sub <16 x i8> %a, %b
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%cond = tail call <16 x i8> @llvm.umin.v16i8(<16 x i8> %sub, <16 x i8> %a)
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ret <16 x i8> %cond
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}
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; Negative test, pattern mismatch : umin(add(a,b),a)
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define i64 @umin_add(i64 %a, i64 %b) {
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; CHECK-LABEL: umin_add
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; CHECK-LABEL: %bb.0
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; CHECK-NEXT: add x8, x0, x1
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; CHECK-NEXT: cmp x8, x0
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; CHECK-NEXT: csel x0, x8, x0, lo
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; CHECK-NEXT: ret
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%add = add i64 %a, %b
149+
%cond = tail call i64 @llvm.umin.i64(i64 %add, i64 %a)
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ret i64 %cond
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}

‎llvm/test/CodeGen/X86/umin-sub-to-usubo-select-combine.ll‎

Lines changed: 156 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,156 @@
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; RUN: llc < %s -mtriple=x86_64 | FileCheck %s
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3+
; GitHub issue #161036
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5+
; Positive test : umin(sub(a,b),a) with scalar types should be folded
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define i64 @underflow_compare_fold_i64(i64 %a, i64 %b) {
7+
; CHECK-LABEL: underflow_compare_fold_i64
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; CHECK-LABEL: %bb.0
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: subq %rsi, %rax
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; CHECK-NEXT: cmovbq %rdi, %rax
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; CHECK-NEXT: retq
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%sub = sub i64 %a, %b
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%cond = tail call i64 @llvm.umin.i64(i64 %sub, i64 %a)
15+
ret i64 %cond
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}
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; Positive test : umin(a,sub(a,b)) with scalar types should be folded
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define i64 @underflow_compare_fold_i64_commute(i64 %a, i64 %b) {
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; CHECK-LABEL: underflow_compare_fold_i64_commute
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; CHECK-LABEL: %bb.0
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: subq %rsi, %rax
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; CHECK-NEXT: cmovbq %rdi, %rax
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; CHECK-NEXT: retq
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%sub = sub i64 %a, %b
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%cond = tail call i64 @llvm.umin.i64(i64 %a, i64 %sub)
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ret i64 %cond
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}
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; Positive test : multi-use is OK since the sub instruction still runs once
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define i64 @underflow_compare_fold_i64_multi_use(i64 %a, i64 %b, ptr addrspace(1) %ptr) {
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; CHECK-LABEL: underflow_compare_fold_i64_multi_use
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; CHECK-LABEL: %bb.0
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: subq %rsi, %rax
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; CHECK-NEXT: movq %rax, (%rdx)
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; CHECK-NEXT: cmovbq %rdi, %rax
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; CHECK-NEXT: retq
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%sub = sub i64 %a, %b
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store i64 %sub, ptr addrspace(1) %ptr
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%cond = call i64 @llvm.umin.i64(i64 %sub, i64 %a)
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ret i64 %cond
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}
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; Positive test : i32
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define i32 @underflow_compare_fold_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: underflow_compare_fold_i32
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; CHECK-LABEL: %bb.0
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: subl %esi, %eax
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; CHECK-NEXT: cmovbl %edi, %eax
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; CHECK-NEXT: retq
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%sub = sub i32 %a, %b
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%cond = tail call i32 @llvm.umin.i32(i32 %sub, i32 %a)
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ret i32 %cond
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}
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; Positive test : i32
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define i32 @underflow_compare_fold_i32_commute(i32 %a, i32 %b) {
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; CHECK-LABEL: underflow_compare_fold_i32_commute
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; CHECK-LABEL: %bb.0
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: subl %esi, %eax
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; CHECK-NEXT: cmovbl %edi, %eax
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; CHECK-NEXT: retq
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%sub = sub i32 %a, %b
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%cond = tail call i32 @llvm.umin.i32(i32 %a, i32 %sub)
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ret i32 %cond
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}
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; Positive test : i32
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define i32 @underflow_compare_fold_i32_multi_use(i32 %a, i32 %b, ptr addrspace(1) %ptr) {
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; CHECK-LABEL: underflow_compare_fold_i32_multi_use
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; CHECK-LABEL: %bb.0
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: subl %esi, %eax
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; CHECK-NEXT: movl %eax, (%rdx)
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; CHECK-NEXT: cmovbl %edi, %eax
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; CHECK-NEXT: retq
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%sub = sub i32 %a, %b
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store i32 %sub, ptr addrspace(1) %ptr
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%cond = call i32 @llvm.umin.i32(i32 %sub, i32 %a)
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ret i32 %cond
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}
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; Positive test : i16
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define i16 @underflow_compare_fold_i16(i16 %a, i16 %b) {
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; CHECK-LABEL: underflow_compare_fold_i16
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; CHECK-LABEL: %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: subw %si, %ax
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; CHECK-NEXT: cmovbl %edi, %eax
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; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
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; CHECK-NEXT: retq
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%sub = sub i16 %a, %b
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%cond = tail call i16 @llvm.umin.i16(i16 %sub, i16 %a)
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ret i16 %cond
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}
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; Positive test : i16
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define i16 @underflow_compare_fold_i16_commute(i16 %a, i16 %b) {
103+
; CHECK-LABEL: underflow_compare_fold_i16_commute
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; CHECK-LABEL: %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: subw %si, %ax
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; CHECK-NEXT: cmovbl %edi, %eax
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; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
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; CHECK-NEXT: retq
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%sub = sub i16 %a, %b
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%cond = tail call i16 @llvm.umin.i16(i16 %a, i16 %sub)
112+
ret i16 %cond
113+
}
114+
115+
; Positive test : i16
116+
define i16 @underflow_compare_fold_i16_multi_use(i16 %a, i16 %b, ptr addrspace(1) %ptr) {
117+
; CHECK-LABEL: underflow_compare_fold_i16_multi_use
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; CHECK-LABEL: %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: subw %si, %ax
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; CHECK-NEXT: movw %ax, (%rdx)
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; CHECK-NEXT: cmovbl %edi, %eax
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; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
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; CHECK-NEXT: retq
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%sub = sub i16 %a, %b
126+
store i16 %sub, ptr addrspace(1) %ptr
127+
%cond = call i16 @llvm.umin.i16(i16 %sub, i16 %a)
128+
ret i16 %cond
129+
}
130+
131+
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; Negative test, vector types : umin(sub(a,b),a) but with vectors
133+
define <16 x i8> @underflow_compare_dontfold_vectors(<16 x i8> %a, <16 x i8> %b) {
134+
; CHECK-LABEL: underflow_compare_dontfold_vectors
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; CHECK-LABEL: %bb.0
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; CHECK-NEXT: movdqa %xmm0, %xmm2
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; CHECK-NEXT: psubb %xmm1, %xmm2
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; CHECK-NEXT: pminub %xmm2, %xmm0
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; CHECK-NEXT: retq
140+
%sub = sub <16 x i8> %a, %b
141+
%cond = tail call <16 x i8> @llvm.umin.v16i8(<16 x i8> %sub, <16 x i8> %a)
142+
ret <16 x i8> %cond
143+
}
144+
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; Negative test, pattern mismatch : umin(add(a,b),a)
146+
define i64 @umin_add(i64 %a, i64 %b) {
147+
; CHECK-LABEL: umin_add
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; CHECK-LABEL: %bb.0
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; CHECK-NEXT: leaq (%rsi,%rdi), %rax
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; CHECK-NEXT: cmpq %rdi, %rax
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; CHECK-NEXT: cmovaeq %rdi, %rax
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; CHECK-NEXT: retq
153+
%add = add i64 %a, %b
154+
%cond = tail call i64 @llvm.umin.i64(i64 %add, i64 %a)
155+
ret i64 %cond
156+
}

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