fixup! respond to review

Author: michaelmaitland

llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

@@ -100,7 +100,7 @@ class RISCVInstructionSelector : public InstructionSelector {
     return selectSHXADD_UWOp(Root, ShAmt);
   }
 
-  ComplexRendererFns selectVLOp(MachineOperand &Root) const;
+  ComplexRendererFns renderVLOp(MachineOperand &Root) const;
 
   // Custom renderers for tablegen
   void renderNegImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
@@ -379,7 +379,7 @@ RISCVInstructionSelector::selectSHXADD_UWOp(MachineOperand &Root,
 }
 
 InstructionSelector::ComplexRendererFns
-RISCVInstructionSelector::selectVLOp(MachineOperand &Root) const {
+RISCVInstructionSelector::renderVLOp(MachineOperand &Root) const {
   MachineRegisterInfo &MRI =
       Root.getParent()->getParent()->getParent()->getRegInfo();
   assert(Root.isReg() && "Expected operand to be a Register");

llvm/lib/Target/RISCV/RISCVGISel.td

@@ -50,9 +50,9 @@ def GIAddrRegImm :
   GIComplexOperandMatcher<s32, "selectAddrRegImm">,
   GIComplexPatternEquiv<AddrRegImm>;
 
-def GIVLOpS32 : GIComplexOperandMatcher<s32, "selectVLOp">,
+def GIVLOpS32 : GIComplexOperandMatcher<s32, "renderVLOp">,
                 GIComplexPatternEquiv<VLOp>;
-def GIVLOpS64 : GIComplexOperandMatcher<s64, "selectVLOp">,
+def GIVLOpS64 : GIComplexOperandMatcher<s64, "renderVLOp">,
                 GIComplexPatternEquiv<VLOp>;
 
 // Convert from i32 immediate to i64 target immediate to make SelectionDAG type

llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-badnegative.mir

@@ -2,12 +2,18 @@
 # RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
 # RUN:   -verify-machineinstrs %s -o - | FileCheck %s
 
+---
 name:            negative_vl
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1:
+    ; CHECK-LABEL: name: negative_vl
+    ; CHECK: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, -2
+    ; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[ADDI]], 0 /* e8 */
+    ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+    ; CHECK-NEXT: PseudoRET implicit $v0
     %0:gprb(s32) = G_CONSTANT i32 -2
     %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
     $v0 = COPY %1(<vscale x 1 x s1>)