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alexrpalexrp
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[llvm] Ensure that soft float targets don't emit fma() libcalls.
The previous behavior could be harmful in some edge cases, such as emitting a call to fma() in the fma() implementation itself. Do this by just being more accurate in isFMAFasterThanFMulAndFAdd(). This was already done for PowerPC; this commit just extends that to Arm, z/Arch, and x86. MIPS and SPARC already got it right, but I added tests for them too, for good measure.
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lines changed

9 files changed

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lines changed

‎llvm/include/llvm/CodeGen/TargetLowering.h‎

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@@ -3240,6 +3240,9 @@ class TargetLoweringBase {
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/// not legal, but should return true if those types will eventually legalize
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/// to types that support FMAs. After legalization, it will only be called on
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/// types that support FMAs (via Legal or Custom actions)
3243+
///
3244+
/// Targets that care about soft float support should return false when soft
3245+
/// float code is being generated (i.e. use-soft-float).
32433246
virtual bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
32443247
EVT) const {
32453248
return false;

‎llvm/lib/Target/ARM/ARMISelLowering.cpp‎

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@@ -19488,6 +19488,9 @@ bool ARMTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
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/// patterns (and we don't have the non-fused floating point instruction).
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bool ARMTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
1949019490
EVT VT) const {
19491+
if (Subtarget->useSoftFloat())
19492+
return false;
19493+
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if (!VT.isSimple())
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return false;
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‎llvm/lib/Target/SystemZ/SystemZISelLowering.cpp‎

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@@ -786,6 +786,9 @@ EVT SystemZTargetLowering::getSetCCResultType(const DataLayout &DL,
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bool SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(
788788
const MachineFunction &MF, EVT VT) const {
789+
if (useSoftFloat())
790+
return false;
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789792
VT = VT.getScalarType();
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791794
if (!VT.isSimple())

‎llvm/lib/Target/X86/X86ISelLowering.cpp‎

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@@ -34645,6 +34645,9 @@ bool X86TargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
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bool X86TargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
3464734647
EVT VT) const {
34648+
if (Subtarget.useSoftFloat())
34649+
return false;
34650+
3464834651
if (!Subtarget.hasAnyFMA())
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return false;
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‎llvm/test/CodeGen/ARM/fmuladd-soft-float.ll‎

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‎llvm/test/CodeGen/Mips/fmuladd-soft-float.ll‎

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‎llvm/test/CodeGen/SPARC/fmuladd-soft-float.ll‎

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‎llvm/test/CodeGen/SystemZ/fmuladd-soft-float.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=s390x --fp-contract off < %s | FileCheck %s -check-prefix=SOFT-FLOAT-FPC-OFF
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; RUN: llc -mtriple=s390x --fp-contract on < %s | FileCheck %s -check-prefix=SOFT-FLOAT-FPC-ON
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; RUN: llc -mtriple=s390x --fp-contract fast < %s | FileCheck %s -check-prefix=SOFT-FLOAT-FPC-FAST
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define float @fmuladd_intrinsic_f32(float %a, float %b, float %c) #0 {
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; SOFT-FLOAT-FPC-OFF-LABEL: fmuladd_intrinsic_f32:
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; SOFT-FLOAT-FPC-OFF: # %bb.0:
9+
; SOFT-FLOAT-FPC-OFF-NEXT: stmg %r13, %r15, 104(%r15)
10+
; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r13, -56
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; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r14, -48
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; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r15, -40
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; SOFT-FLOAT-FPC-OFF-NEXT: aghi %r15, -160
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; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_def_cfa_offset 320
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; SOFT-FLOAT-FPC-OFF-NEXT: llgfr %r2, %r2
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; SOFT-FLOAT-FPC-OFF-NEXT: llgfr %r3, %r3
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; SOFT-FLOAT-FPC-OFF-NEXT: lr %r13, %r4
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; SOFT-FLOAT-FPC-OFF-NEXT: brasl %r14, __mulsf3@PLT
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; SOFT-FLOAT-FPC-OFF-NEXT: llgfr %r3, %r13
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; SOFT-FLOAT-FPC-OFF-NEXT: brasl %r14, __addsf3@PLT
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; SOFT-FLOAT-FPC-OFF-NEXT: # kill: def $r2l killed $r2l killed $r2d
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; SOFT-FLOAT-FPC-OFF-NEXT: lmg %r13, %r15, 264(%r15)
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; SOFT-FLOAT-FPC-OFF-NEXT: br %r14
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;
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; SOFT-FLOAT-FPC-ON-LABEL: fmuladd_intrinsic_f32:
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; SOFT-FLOAT-FPC-ON: # %bb.0:
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; SOFT-FLOAT-FPC-ON-NEXT: stmg %r13, %r15, 104(%r15)
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; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r13, -56
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; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r14, -48
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; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r15, -40
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; SOFT-FLOAT-FPC-ON-NEXT: aghi %r15, -160
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; SOFT-FLOAT-FPC-ON-NEXT: .cfi_def_cfa_offset 320
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; SOFT-FLOAT-FPC-ON-NEXT: llgfr %r2, %r2
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; SOFT-FLOAT-FPC-ON-NEXT: llgfr %r3, %r3
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; SOFT-FLOAT-FPC-ON-NEXT: lr %r13, %r4
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; SOFT-FLOAT-FPC-ON-NEXT: brasl %r14, __mulsf3@PLT
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; SOFT-FLOAT-FPC-ON-NEXT: llgfr %r3, %r13
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; SOFT-FLOAT-FPC-ON-NEXT: brasl %r14, __addsf3@PLT
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; SOFT-FLOAT-FPC-ON-NEXT: # kill: def $r2l killed $r2l killed $r2d
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; SOFT-FLOAT-FPC-ON-NEXT: lmg %r13, %r15, 264(%r15)
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; SOFT-FLOAT-FPC-ON-NEXT: br %r14
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;
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; SOFT-FLOAT-FPC-FAST-LABEL: fmuladd_intrinsic_f32:
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; SOFT-FLOAT-FPC-FAST: # %bb.0:
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; SOFT-FLOAT-FPC-FAST-NEXT: stmg %r13, %r15, 104(%r15)
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; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r13, -56
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; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r14, -48
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; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r15, -40
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; SOFT-FLOAT-FPC-FAST-NEXT: aghi %r15, -160
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; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_def_cfa_offset 320
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; SOFT-FLOAT-FPC-FAST-NEXT: llgfr %r2, %r2
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; SOFT-FLOAT-FPC-FAST-NEXT: llgfr %r3, %r3
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; SOFT-FLOAT-FPC-FAST-NEXT: lr %r13, %r4
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; SOFT-FLOAT-FPC-FAST-NEXT: brasl %r14, __mulsf3@PLT
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; SOFT-FLOAT-FPC-FAST-NEXT: llgfr %r3, %r13
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; SOFT-FLOAT-FPC-FAST-NEXT: brasl %r14, __addsf3@PLT
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; SOFT-FLOAT-FPC-FAST-NEXT: # kill: def $r2l killed $r2l killed $r2d
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; SOFT-FLOAT-FPC-FAST-NEXT: lmg %r13, %r15, 264(%r15)
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; SOFT-FLOAT-FPC-FAST-NEXT: br %r14
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%result = call float @llvm.fmuladd.f32(float %a, float %b, float %c)
61+
ret float %result
62+
}
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define double @fmuladd_intrinsic_f64(double %a, double %b, double %c) #0 {
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; SOFT-FLOAT-FPC-OFF-LABEL: fmuladd_intrinsic_f64:
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; SOFT-FLOAT-FPC-OFF: # %bb.0:
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; SOFT-FLOAT-FPC-OFF-NEXT: stmg %r13, %r15, 104(%r15)
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; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r13, -56
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; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r14, -48
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; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r15, -40
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; SOFT-FLOAT-FPC-OFF-NEXT: aghi %r15, -160
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; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_def_cfa_offset 320
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; SOFT-FLOAT-FPC-OFF-NEXT: lgr %r13, %r4
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; SOFT-FLOAT-FPC-OFF-NEXT: brasl %r14, __muldf3@PLT
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; SOFT-FLOAT-FPC-OFF-NEXT: lgr %r3, %r13
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; SOFT-FLOAT-FPC-OFF-NEXT: brasl %r14, __adddf3@PLT
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; SOFT-FLOAT-FPC-OFF-NEXT: lmg %r13, %r15, 264(%r15)
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; SOFT-FLOAT-FPC-OFF-NEXT: br %r14
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;
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; SOFT-FLOAT-FPC-ON-LABEL: fmuladd_intrinsic_f64:
81+
; SOFT-FLOAT-FPC-ON: # %bb.0:
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; SOFT-FLOAT-FPC-ON-NEXT: stmg %r13, %r15, 104(%r15)
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; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r13, -56
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; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r14, -48
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; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r15, -40
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; SOFT-FLOAT-FPC-ON-NEXT: aghi %r15, -160
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; SOFT-FLOAT-FPC-ON-NEXT: .cfi_def_cfa_offset 320
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; SOFT-FLOAT-FPC-ON-NEXT: lgr %r13, %r4
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; SOFT-FLOAT-FPC-ON-NEXT: brasl %r14, __muldf3@PLT
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; SOFT-FLOAT-FPC-ON-NEXT: lgr %r3, %r13
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; SOFT-FLOAT-FPC-ON-NEXT: brasl %r14, __adddf3@PLT
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; SOFT-FLOAT-FPC-ON-NEXT: lmg %r13, %r15, 264(%r15)
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; SOFT-FLOAT-FPC-ON-NEXT: br %r14
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;
95+
; SOFT-FLOAT-FPC-FAST-LABEL: fmuladd_intrinsic_f64:
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; SOFT-FLOAT-FPC-FAST: # %bb.0:
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; SOFT-FLOAT-FPC-FAST-NEXT: stmg %r13, %r15, 104(%r15)
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; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r13, -56
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; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r14, -48
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; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r15, -40
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; SOFT-FLOAT-FPC-FAST-NEXT: aghi %r15, -160
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; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_def_cfa_offset 320
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; SOFT-FLOAT-FPC-FAST-NEXT: lgr %r13, %r4
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; SOFT-FLOAT-FPC-FAST-NEXT: brasl %r14, __muldf3@PLT
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; SOFT-FLOAT-FPC-FAST-NEXT: lgr %r3, %r13
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; SOFT-FLOAT-FPC-FAST-NEXT: brasl %r14, __adddf3@PLT
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; SOFT-FLOAT-FPC-FAST-NEXT: lmg %r13, %r15, 264(%r15)
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; SOFT-FLOAT-FPC-FAST-NEXT: br %r14
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%result = call double @llvm.fmuladd.f64(double %a, double %b, double %c)
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ret double %result
111+
}
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define float @fmuladd_contract_f32(float %a, float %b, float %c) #0 {
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; SOFT-FLOAT-FPC-OFF-LABEL: fmuladd_contract_f32:
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; SOFT-FLOAT-FPC-OFF: # %bb.0:
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; SOFT-FLOAT-FPC-OFF-NEXT: stmg %r13, %r15, 104(%r15)
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; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r13, -56
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; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r14, -48
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; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r15, -40
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; SOFT-FLOAT-FPC-OFF-NEXT: aghi %r15, -160
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; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_def_cfa_offset 320
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; SOFT-FLOAT-FPC-OFF-NEXT: llgfr %r2, %r2
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; SOFT-FLOAT-FPC-OFF-NEXT: llgfr %r3, %r3
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; SOFT-FLOAT-FPC-OFF-NEXT: lr %r13, %r4
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; SOFT-FLOAT-FPC-OFF-NEXT: brasl %r14, __mulsf3@PLT
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; SOFT-FLOAT-FPC-OFF-NEXT: llgfr %r3, %r13
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; SOFT-FLOAT-FPC-OFF-NEXT: brasl %r14, __addsf3@PLT
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; SOFT-FLOAT-FPC-OFF-NEXT: # kill: def $r2l killed $r2l killed $r2d
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; SOFT-FLOAT-FPC-OFF-NEXT: lmg %r13, %r15, 264(%r15)
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; SOFT-FLOAT-FPC-OFF-NEXT: br %r14
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;
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; SOFT-FLOAT-FPC-ON-LABEL: fmuladd_contract_f32:
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; SOFT-FLOAT-FPC-ON: # %bb.0:
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; SOFT-FLOAT-FPC-ON-NEXT: stmg %r13, %r15, 104(%r15)
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; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r13, -56
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; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r14, -48
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; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r15, -40
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; SOFT-FLOAT-FPC-ON-NEXT: aghi %r15, -160
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; SOFT-FLOAT-FPC-ON-NEXT: .cfi_def_cfa_offset 320
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; SOFT-FLOAT-FPC-ON-NEXT: llgfr %r2, %r2
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; SOFT-FLOAT-FPC-ON-NEXT: llgfr %r3, %r3
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; SOFT-FLOAT-FPC-ON-NEXT: lr %r13, %r4
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; SOFT-FLOAT-FPC-ON-NEXT: brasl %r14, __mulsf3@PLT
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; SOFT-FLOAT-FPC-ON-NEXT: llgfr %r3, %r13
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; SOFT-FLOAT-FPC-ON-NEXT: brasl %r14, __addsf3@PLT
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; SOFT-FLOAT-FPC-ON-NEXT: # kill: def $r2l killed $r2l killed $r2d
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; SOFT-FLOAT-FPC-ON-NEXT: lmg %r13, %r15, 264(%r15)
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; SOFT-FLOAT-FPC-ON-NEXT: br %r14
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;
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; SOFT-FLOAT-FPC-FAST-LABEL: fmuladd_contract_f32:
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; SOFT-FLOAT-FPC-FAST: # %bb.0:
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; SOFT-FLOAT-FPC-FAST-NEXT: stmg %r13, %r15, 104(%r15)
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; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r13, -56
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; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r14, -48
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; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r15, -40
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; SOFT-FLOAT-FPC-FAST-NEXT: aghi %r15, -160
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; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_def_cfa_offset 320
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; SOFT-FLOAT-FPC-FAST-NEXT: llgfr %r2, %r2
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; SOFT-FLOAT-FPC-FAST-NEXT: llgfr %r3, %r3
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; SOFT-FLOAT-FPC-FAST-NEXT: lr %r13, %r4
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; SOFT-FLOAT-FPC-FAST-NEXT: brasl %r14, __mulsf3@PLT
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; SOFT-FLOAT-FPC-FAST-NEXT: llgfr %r3, %r13
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; SOFT-FLOAT-FPC-FAST-NEXT: brasl %r14, __addsf3@PLT
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; SOFT-FLOAT-FPC-FAST-NEXT: # kill: def $r2l killed $r2l killed $r2d
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; SOFT-FLOAT-FPC-FAST-NEXT: lmg %r13, %r15, 264(%r15)
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; SOFT-FLOAT-FPC-FAST-NEXT: br %r14
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%product = fmul float %a, %b
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%result = fadd float %product, %c
169+
ret float %result
170+
}
171+
172+
define double @fmuladd_contract_f64(double %a, double %b, double %c) #0 {
173+
; SOFT-FLOAT-FPC-OFF-LABEL: fmuladd_contract_f64:
174+
; SOFT-FLOAT-FPC-OFF: # %bb.0:
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; SOFT-FLOAT-FPC-OFF-NEXT: stmg %r13, %r15, 104(%r15)
176+
; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r13, -56
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; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r14, -48
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; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_offset %r15, -40
179+
; SOFT-FLOAT-FPC-OFF-NEXT: aghi %r15, -160
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; SOFT-FLOAT-FPC-OFF-NEXT: .cfi_def_cfa_offset 320
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; SOFT-FLOAT-FPC-OFF-NEXT: lgr %r13, %r4
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; SOFT-FLOAT-FPC-OFF-NEXT: brasl %r14, __muldf3@PLT
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; SOFT-FLOAT-FPC-OFF-NEXT: lgr %r3, %r13
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; SOFT-FLOAT-FPC-OFF-NEXT: brasl %r14, __adddf3@PLT
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; SOFT-FLOAT-FPC-OFF-NEXT: lmg %r13, %r15, 264(%r15)
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; SOFT-FLOAT-FPC-OFF-NEXT: br %r14
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;
188+
; SOFT-FLOAT-FPC-ON-LABEL: fmuladd_contract_f64:
189+
; SOFT-FLOAT-FPC-ON: # %bb.0:
190+
; SOFT-FLOAT-FPC-ON-NEXT: stmg %r13, %r15, 104(%r15)
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; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r13, -56
192+
; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r14, -48
193+
; SOFT-FLOAT-FPC-ON-NEXT: .cfi_offset %r15, -40
194+
; SOFT-FLOAT-FPC-ON-NEXT: aghi %r15, -160
195+
; SOFT-FLOAT-FPC-ON-NEXT: .cfi_def_cfa_offset 320
196+
; SOFT-FLOAT-FPC-ON-NEXT: lgr %r13, %r4
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; SOFT-FLOAT-FPC-ON-NEXT: brasl %r14, __muldf3@PLT
198+
; SOFT-FLOAT-FPC-ON-NEXT: lgr %r3, %r13
199+
; SOFT-FLOAT-FPC-ON-NEXT: brasl %r14, __adddf3@PLT
200+
; SOFT-FLOAT-FPC-ON-NEXT: lmg %r13, %r15, 264(%r15)
201+
; SOFT-FLOAT-FPC-ON-NEXT: br %r14
202+
;
203+
; SOFT-FLOAT-FPC-FAST-LABEL: fmuladd_contract_f64:
204+
; SOFT-FLOAT-FPC-FAST: # %bb.0:
205+
; SOFT-FLOAT-FPC-FAST-NEXT: stmg %r13, %r15, 104(%r15)
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; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r13, -56
207+
; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r14, -48
208+
; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_offset %r15, -40
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; SOFT-FLOAT-FPC-FAST-NEXT: aghi %r15, -160
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; SOFT-FLOAT-FPC-FAST-NEXT: .cfi_def_cfa_offset 320
211+
; SOFT-FLOAT-FPC-FAST-NEXT: lgr %r13, %r4
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; SOFT-FLOAT-FPC-FAST-NEXT: brasl %r14, __muldf3@PLT
213+
; SOFT-FLOAT-FPC-FAST-NEXT: lgr %r3, %r13
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; SOFT-FLOAT-FPC-FAST-NEXT: brasl %r14, __adddf3@PLT
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; SOFT-FLOAT-FPC-FAST-NEXT: lmg %r13, %r15, 264(%r15)
216+
; SOFT-FLOAT-FPC-FAST-NEXT: br %r14
217+
%product = fmul double %a, %b
218+
%result = fadd double %product, %c
219+
ret double %result
220+
}
221+
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attributes #0 = { "use-soft-float"="true" }
223+
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declare float @llvm.fmuladd.f32(float %a, float %b, float %c)
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declare double @llvm.fmuladd.f64(double %a, double %b, double %c)

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