[PowerPC] Do not rely on MachineSink threshold to optimize CR spilling

spill_p0_setb.ll and knowCRBitSpill.ll rely on a probability threshold
in MachineSink to pull down CRSET/CRUNSET. It's worth to do so anyway
and let register allocation decide otherwise.
Additionally, make the interface accept a const MI.

Author: guy-david

llvm/include/llvm/CodeGen/TargetInstrInfo.h

@@ -165,7 +165,7 @@ class TargetInstrInfo : public MCInstrInfo {
 
   /// For a "cheap" instruction which doesn't enable additional sinking,
   /// should MachineSink break a critical edge to sink it anyways?
-  virtual bool shouldBreakCriticalEdgeToSink(MachineInstr &MI) const {
+  virtual bool shouldBreakCriticalEdgeToSink(const MachineInstr &MI) const {
     return false;
   }
 

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

@@ -1072,6 +1072,13 @@ Register PPCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
   return 0;
 }
 
+/// Sink down CodeGen-only, cheap instructions to allow further
+/// optimizations which are only applied intra-block.
+bool PPCInstrInfo::shouldBreakCriticalEdgeToSink(const MachineInstr &MI) const {
+  // These can turn into immediates, see PPCRegisterInfo::lowerCRBitRestore.
+  return MI.getOpcode() == PPC::CRSET || MI.getOpcode() == PPC::CRUNSET;
+}
+
 // For opcodes with the ReMaterializable flag set, this function is called to
 // verify the instruction is really rematable.
 bool PPCInstrInfo::isReallyTriviallyReMaterializable(

llvm/lib/Target/PowerPC/PPCInstrInfo.h

@@ -424,6 +424,7 @@ class PPCInstrInfo : public PPCGenInstrInfo {
                              unsigned &SubIdx) const override;
   Register isLoadFromStackSlot(const MachineInstr &MI,
                                int &FrameIndex) const override;
+  bool shouldBreakCriticalEdgeToSink(const MachineInstr &MI) const override;
   bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
   Register isStoreToStackSlot(const MachineInstr &MI,
                               int &FrameIndex) const override;

llvm/lib/Target/RISCV/RISCVInstrInfo.h

@@ -78,7 +78,7 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
 
   bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
 
-  bool shouldBreakCriticalEdgeToSink(MachineInstr &MI) const override {
+  bool shouldBreakCriticalEdgeToSink(const MachineInstr &MI) const override {
     return MI.getOpcode() == RISCV::ADDI && MI.getOperand(1).isReg() &&
            MI.getOperand(1).getReg() == RISCV::X0;
   }

llvm/test/CodeGen/PowerPC/spill_p9_setb.ll

@@ -16,21 +16,21 @@
 
 define void @p9_setb_spill() {
 ; CHECK-P9-LABEL: p9_setb_spill:
-; CHECK-P9:       # %bb.1: # %if.then
+; CHECK-P9:       # %if.then
 ; CHECK-P9-DAG:    crnot 4*cr[[CREG:.*]]+lt, eq
 ; CHECK-P9-DAG:    setb [[REG1:.*]], cr[[CREG]]
 ; CHECK-P9-DAG:    stw [[REG1]]
 ; CHECK-P9:        blr
-; CHECK-P9:        .LBB0_4: # %if.then1
+; CHECK-P9:       # %if.then1
 ;
 ; CHECK-P8-LABEL: p9_setb_spill:
-; CHECK-P8:       # %bb.1: # %if.then
+; CHECK-P8:       # %if.then
 ; CHECK-P8-DAG:    crnot 4*cr[[CREG2:.*]]+lt, eq
 ; CHECK-P8-DAG:    mfocrf [[REG2:.*]],
 ; CHECK-P8-DAG:    rlwinm [[REG2]], [[REG2]]
 ; CHECK-P8-DAG:    stw [[REG2]]
 ; CHECK-P8:        blr
-; CHECK-P8:        .LBB0_4: # %if.then1
+; CHECK-P8:       # %if.then1
 entry:
   br i1 undef, label %if.end, label %if.then