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vitalybukavitalybuka
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Created using spr 1.3.6
2 parents 72a9595 + 769c2b3 commit 20648e0

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‎.github/new-prs-labeler.yml‎

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@@ -722,7 +722,12 @@ mlgo:
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- llvm/include/llvm/Analysis/IR2Vec.h
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- llvm/lib/Analysis/IR2Vec.cpp
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- llvm/lib/Analysis/models/**
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- llvm/include/llvm/CodeGen/MIR2Vec.h
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- llvm/lib/CodeGen/MIR2Vec.cpp
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- llvm/test/Analysis/IR2Vec/**
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- llvm/test/CodeGen/MIR2Vec/**
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- llvm/unittests/Analysis/IR2VecTest.cpp
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- llvm/unittests/CodeGen/MIR2VecTest.cpp
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- llvm/tools/llvm-ir2vec/**
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- llvm/docs/CommandGuide/llvm-ir2vec.rst
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‎clang/test/Driver/print-supported-extensions-riscv.c‎

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@@ -216,7 +216,7 @@
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// CHECK-NEXT: zibi 0.1 'Zibi' (Branch with Immediate)
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// CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad)
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// CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack)
219-
// CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions)
219+
// CHECK-NEXT: zalasr 0.9 'Zalasr' (Load-Acquire and Store-Release Instructions)
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// CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)
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// CHECK-NEXT: zvfbfa 0.1 'Zvfbfa' (Additional BF16 vector compute support)
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// CHECK-NEXT: zvfofp8min 0.2 'Zvfofp8min' (Vector OFP8 Converts)

‎clang/test/Driver/riscv-arch.c‎

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@@ -384,9 +384,9 @@
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// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr0p7 -menable-experimental-extensions -### %s \
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// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s
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// RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izalasr0p7'
387-
// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.7 for experimental extension 'zalasr' (this compiler supports 0.1)
387+
// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.7 for experimental extension 'zalasr' (this compiler supports 0.9)
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389-
// RUN: %clang --target=riscv32-unknown-elf -march=rv32izalasr0p1 -menable-experimental-extensions -### %s \
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// RUN: %clang --target=riscv32-unknown-elf -march=rv32izalasr0p9 -menable-experimental-extensions -### %s \
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// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s
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// RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zalasr"
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‎clang/test/Preprocessor/riscv-target-features.c‎

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@@ -1531,12 +1531,12 @@
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// Experimental extensions
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// RUN: %clang --target=riscv32 -menable-experimental-extensions \
1534-
// RUN: -march=rv32i_zalasr0p1 -E -dM %s \
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// RUN: -march=rv32i_zalasr0p9 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
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// RUN: %clang --target=riscv64 -menable-experimental-extensions \
1537-
// RUN: -march=rv64i_zalasr0p1 -E -dM %s \
1537+
// RUN: -march=rv64i_zalasr0p9 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
1539-
// CHECK-ZALASR-EXT: __riscv_zalasr 1000{{$}}
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// CHECK-ZALASR-EXT: __riscv_zalasr 9000{{$}}
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// RUN: %clang --target=riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32izfbfmin1p0 -E -dM %s \

‎compiler-rt/lib/builtins/cpu_model/aarch64/fmv/android.inc‎

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Original file line numberDiff line numberDiff line change
@@ -27,8 +27,8 @@ void CONSTRUCTOR_ATTRIBUTE __init_cpu_features(void) {
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2828
unsigned long hwcap = getauxval(AT_HWCAP);
2929
unsigned long hwcap2 = getauxval(AT_HWCAP2);
30-
unsigned long hwcap2 = getauxval(AT_HWCAP3);
31-
unsigned long hwcap2 = getauxval(AT_HWCAP4);
30+
unsigned long hwcap3 = getauxval(AT_HWCAP3);
31+
unsigned long hwcap4 = getauxval(AT_HWCAP4);
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__ifunc_arg_t arg;
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arg._size = sizeof(__ifunc_arg_t);

‎compiler-rt/lib/builtins/cpu_model/aarch64/fmv/getauxval.inc‎

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@@ -12,8 +12,8 @@ void CONSTRUCTOR_ATTRIBUTE __init_cpu_features(void) {
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1313
unsigned long hwcap = getauxval(AT_HWCAP);
1414
unsigned long hwcap2 = getauxval(AT_HWCAP2);
15-
unsigned long hwcap2 = getauxval(AT_HWCAP3);
16-
unsigned long hwcap2 = getauxval(AT_HWCAP4);
15+
unsigned long hwcap3 = getauxval(AT_HWCAP3);
16+
unsigned long hwcap4 = getauxval(AT_HWCAP4);
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__ifunc_arg_t arg;
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arg._size = sizeof(__ifunc_arg_t);

‎lldb/test/API/functionalities/unwind/cortex-m-exception/TestCortexMExceptionUnwind.py‎

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@@ -12,21 +12,6 @@
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class TestCortexMExceptionUnwind(TestBase):
1313
NO_DEBUG_INFO_TESTCASE = True
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15-
# on the lldb-remote-linux-ubuntu CI, the binary.json's triple of
16-
# armv7m-apple is not being set in the Target triple, and we're
17-
# picking the wrong ABI plugin, ABISysV_arm.
18-
# ABISysV_arm::CreateDefaultUnwindPlan() doesn't have a way to detect
19-
# arm/thumb for a stack frame, or even the Target's triple for a
20-
# Cortex-M part that is always thumb. It hardcodes r11 as the frame
21-
# pointer register, which is correct for arm code but not thumb.
22-
# It is never correct # on a Cortex-M target.
23-
# The Darwin ABIMacOSX_arm diverges from AAPCS and always uses r7 for
24-
# the frame pointer -- the thumb convention -- whether executing arm or
25-
# thumb. So its CreateDefaultUnwindPlan picks the correct register for
26-
# the frame pointer, and we can walk the stack.
27-
# ABISysV_arm::CreateDefaultUnwindPlan will only get one frame and
28-
# not be able to continue.
29-
@skipIfRemote
3015
def test_no_fpu(self):
3116
"""Test that we can backtrace correctly through an ARM Cortex-M Exception return stack"""
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@@ -59,9 +44,8 @@ def test_no_fpu(self):
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# frames above that. The topmost two stack frames
6045
# were not interesting for this test, so I didn't
6146
# create symbols for them.
62-
self.assertEqual(thread.GetNumFrames(), 6)
47+
self.assertEqual(thread.GetNumFrames(), 3)
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stackframe_names = [
64-
"exception_catcher",
6549
"exception_catcher",
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"exception_thrower",
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"main",

‎lldb/test/API/functionalities/unwind/cortex-m-exception/armv7m-nofpu-exception.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@ cpu: armv7m
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threads:
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- regsets:
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- flavor: gpr
5-
registers: [{name: sp, value: 0x2000fe70}, {name: r7, value: 0x2000fe80},
6-
{name: pc, value: 0x0020392c}, {name: lr, value: 0x0020392d}]
5+
registers: [{name: sp, value: 0x2000fe88}, {name: r7, value: 0x2000fe88},
6+
{name: pc, value: 0x00203916}, {name: lr, value: 0x0020392d}]
77
memory-regions:
88
# stack memory fetched via
99
# (lldb) p/x $sp
@@ -14,7 +14,7 @@ memory-regions:
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0x0000002a, 0x20010e58, 0x00203923, 0x00000001,
1515
0x2000fe88, 0x00203911, 0x2000ffdc, 0xfffffff9,
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0x00000102, 0x00000002, 0x000003f0, 0x0000002a,
17-
0x20012620, 0x00203215, 0x00203366, 0x81000200,
17+
0x20012620, 0x00203215, 0x00202a92, 0x81000200,
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0x00203215, 0x200128b0, 0x0024928d, 0x2000fecc,
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0x002491ed, 0x20010e58, 0x20010e4c, 0x2000ffa0,
2020
0x200107a0, 0x0000003c, 0x200116e8, 0x200108b0,
@@ -62,3 +62,26 @@ memory-regions:
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0x98, 0xae, 0x28, 0x00
6363
]
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65+
# exception_thrower
66+
# (lldb) disass -b -c 12 -n exception_thrower
67+
# 0x202a88 <+0>: 0xb5f0 push {r4, r5, r6, r7, lr}
68+
# 0x202a8a <+2>: 0xaf03 add r7, sp, #0xc
69+
# 0x202a8c <+4>: 0xe92d0f00 push.w {r8, r9, r10, r11}
70+
# 0x202a90 <+8>: 0xb0c3 sub sp, #0x10c
71+
# 0x202a92 <+10>: 0xf7ffffd9 bl 0x202a48
72+
- addr: 0x202a88
73+
UInt8: [
74+
0xf0, 0xb5, 0x03, 0xaf, 0x2d, 0xe9, 0x00, 0x0f,
75+
0xc3, 0xb0, 0xff, 0xf7, 0xd9, 0xff, 0xff, 0xf7
76+
]
77+
78+
# main:
79+
# 0x202a7e <+0>: push {r7, lr}
80+
# 0x202a80 <+2>: mov r7, sp
81+
# 0x202a82 <+4>: bl 0x202a88 ; exception_thrower
82+
# 0x202a86 <+8>: nop
83+
- addr: 0x202a7e
84+
UInt8: [
85+
0x80, 0xb5, 0x6f, 0x46, 0x00, 0xf0, 0x01, 0xf8,
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0x00, 0xbf
87+
]

‎lldb/test/API/functionalities/unwind/cortex-m-exception/binary.json‎

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@@ -1,5 +1,5 @@
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{
2-
"triple": "armv7m-apple",
2+
"triple": "armv7m--",
33
"uuid": "2D157DBA-53C9-3AC7-B5A1-9D336EC831CB",
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"type": "executable",
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"sections": [
@@ -28,13 +28,13 @@
2828
{
2929
"name": "exception_catcher",
3030
"type": "code",
31-
"size": 44,
31+
"size": 32,
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"address": 2111760
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},
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{
3535
"name": "exception_thrower",
3636
"type": "code",
37-
"size": 2652,
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"size": 16,
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"address": 2108040
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}
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]

‎llvm/docs/RISCVUsage.rst‎

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@@ -334,7 +334,7 @@ LLVM supports (to various degrees) a number of experimental extensions. All exp
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The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases. Experimental extensions are expected to either transition to ratified status, or be eventually removed. The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised.
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336336
``experimental-zalasr``
337-
LLVM implements the `0.0.5 draft specification <https://github.com/mehnadnerd/riscv-zalasr>`__.
337+
LLVM implements the `0.9 draft specification <https://github.com/riscv/riscv-zalasr/releases/tag/v0.9>`__.
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339339
``experimental-zibi``
340340
LLVM implements the `0.1 release specification <https://github.com/riscv/zibi/releases/tag/v0.1.0>`__.

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