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[RISCV] Add back SiFive's cdiscard.d.l1, cflush.d.l1, and cease instructions. (#83896)
These were in LLVM 17 but removed from LLVM 18 due to an incorrect extension name being used. This restores them with new extension names that match SiFive's downstream compiler. The extension name has been used internally for some time. It uses XSiFive instead of XSf like the newer extensions. `cease` did not have an internal extension name so its using the `XSf` convention. The spec for the instructions is here https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf though the extension name is not listed. Column width in the extension printing had to be changed to accommodate a longer extension name.
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‎clang/test/Preprocessor/riscv-target-features.c‎

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@@ -56,11 +56,14 @@
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// CHECK-NOT: __riscv_xcvmac {{.*$}}
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// CHECK-NOT: __riscv_xcvmem {{.*$}}
5858
// CHECK-NOT: __riscv_xcvsimd {{.*$}}
59+
// CHECK-NOT: __riscv_xsfcease {{.*$}}
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// CHECK-NOT: __riscv_xsfvcp {{.*$}}
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// CHECK-NOT: __riscv_xsfvfnrclipxfqf {{.*$}}
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// CHECK-NOT: __riscv_xsfvfwmaccqqq {{.*$}}
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// CHECK-NOT: __riscv_xsfqmaccdod {{.*$}}
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// CHECK-NOT: __riscv_xsfvqmaccqoq {{.*$}}
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// CHECK-NOT: __riscv_xsifivecdiscarddlone {{.*$}}
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// CHECK-NOT: __riscv_xsifivecflushdlone {{.*$}}
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// CHECK-NOT: __riscv_xtheadba {{.*$}}
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// CHECK-NOT: __riscv_xtheadbb {{.*$}}
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// CHECK-NOT: __riscv_xtheadbs {{.*$}}
@@ -517,6 +520,14 @@
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// RUN: -o - | FileCheck --check-prefix=CHECK-XCVSIMD-EXT %s
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// CHECK-XCVSIMD-EXT: __riscv_xcvsimd 1000000{{$}}
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32ixsfcease -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XSFCEASE-EXT %s
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// RUN: %clang --target=riscv64-unknown-linux-gnu \
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// RUN: -march=rv64ixsfcease -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XSFCEASE-EXT %s
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// CHECK-XSFCEASE-EXT: __riscv_xsfcease 1000000{{$}}
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32ixsfvcp -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVCP-EXT %s
@@ -557,6 +568,22 @@
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// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVQMACCQOQ-EXT %s
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// CHECK-XSFVQMACCQOQ-EXT: __riscv_xsfvqmaccqoq 1000000{{$}}
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32ixsifivecdiscarddlone -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
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// RUN: %clang --target=riscv64-unknown-linux-gnu \
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// RUN: -march=rv64ixsifivecdiscarddlone -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
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// CHECK-XSIFIVECDISCARDDLONE-EXT: __riscv_xsifivecdiscarddlone 1000000{{$}}
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32ixsifivecflushdlone -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
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// RUN: %clang --target=riscv64-unknown-linux-gnu \
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// RUN: -march=rv64ixsifivecflushdlone -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
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// CHECK-XSIFIVECFLUSHDLONE-EXT: __riscv_xsifivecflushdlone 1000000{{$}}
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32ixtheadba -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XTHEADBA-EXT %s

‎llvm/docs/RISCVUsage.rst‎

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@@ -362,6 +362,15 @@ The current vendor extensions supported are:
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``XCVbi``
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LLVM implements `version 1.0.0 of the CORE-V immediate branching custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/cv32e40p_v1.3.2/docs/source/instruction_set_extensions.rst>`__ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.
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``XSiFivecdiscarddlone``
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LLVM implements `the SiFive sf.cdiscard.d.l1 instruction specified in <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.
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``XSiFivecflushdlone``
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LLVM implements `the SiFive sf.cflush.d.l1 instruction specified in <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.
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``XSfcease``
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LLVM implements `the SiFive sf.cease instruction specified in <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.
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Experimental C Intrinsics
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=========================
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‎llvm/lib/Support/RISCVISAInfo.cpp‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -90,11 +90,14 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
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{"xcvmac", {1, 0}},
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{"xcvmem", {1, 0}},
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{"xcvsimd", {1, 0}},
93+
{"xsfcease", {1, 0}},
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{"xsfvcp", {1, 0}},
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{"xsfvfnrclipxfqf", {1, 0}},
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{"xsfvfwmaccqqq", {1, 0}},
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{"xsfvqmaccdod", {1, 0}},
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{"xsfvqmaccqoq", {1, 0}},
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{"xsifivecdiscarddlone", {1, 0}},
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{"xsifivecflushdlone", {1, 0}},
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{"xtheadba", {1, 0}},
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{"xtheadbb", {1, 0}},
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{"xtheadbs", {1, 0}},
@@ -258,7 +261,7 @@ static void PrintExtension(StringRef Name, StringRef Version,
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StringRef Description) {
259262
outs().indent(4);
260263
unsigned VersionWidth = Description.empty() ? 0 : 10;
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outs() << left_justify(Name, 20) << left_justify(Version, VersionWidth)
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outs() << left_justify(Name, 21) << left_justify(Version, VersionWidth)
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<< Description << "\n";
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}
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‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

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@@ -595,6 +595,14 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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TRY_TO_DECODE_FEATURE(
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RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32,
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"SiFive FP32-to-int8 Ranged Clip Instructions opcode table");
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TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecdiscarddlone,
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DecoderTableXSiFivecdiscarddlone32,
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"SiFive sf.cdiscard.d.l1 custom opcode table");
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TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecflushdlone,
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DecoderTableXSiFivecflushdlone32,
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"SiFive sf.cflush.d.l1 custom opcode table");
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TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcease, DecoderTableXSfcease32,
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"SiFive sf.cease custom opcode table");
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TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
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DecoderTableXCVbitmanip32,
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"CORE-V Bit Manipulation custom opcode table");

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

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@@ -1058,6 +1058,30 @@ def HasVendorXSfvfnrclipxfqf
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AssemblerPredicate<(all_of FeatureVendorXSfvfnrclipxfqf),
10591059
"'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)">;
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def FeatureVendorXSiFivecdiscarddlone
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: SubtargetFeature<"xsifivecdiscarddlone", "HasVendorXSiFivecdiscarddlone", "true",
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"'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)", []>;
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def HasVendorXSiFivecdiscarddlone
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: Predicate<"Subtarget->hasVendorXSiFivecdiscarddlone()">,
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AssemblerPredicate<(all_of FeatureVendorXSiFivecdiscarddlone),
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"'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)">;
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def FeatureVendorXSiFivecflushdlone
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: SubtargetFeature<"xsifivecflushdlone", "HasVendorXSiFivecflushdlone", "true",
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"'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)", []>;
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def HasVendorXSiFivecflushdlone
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: Predicate<"Subtarget->hasVendorXSiFivecflushdlone()">,
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AssemblerPredicate<(all_of FeatureVendorXSiFivecflushdlone),
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"'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)">;
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def FeatureVendorXSfcease
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: SubtargetFeature<"xsfcease", "HasVendorXSfcease", "true",
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"'XSfcease' (SiFive sf.cease Instruction)", []>;
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def HasVendorXSfcease
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: Predicate<"Subtarget->hasVendorXSfcease()">,
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AssemblerPredicate<(all_of FeatureVendorXSfcease),
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"'XSfcease' (SiFive sf.cease Instruction)">;
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// Core-V Extensions
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def FeatureVendorXCVelw

‎llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td‎

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@@ -808,3 +808,35 @@ let Predicates = [HasVendorXSfvfnrclipxfqf] in {
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defm : VPatVFNRCLIP<"vfnrclip_xu_f_qf", "VFNRCLIP_XU_F_QF">;
809809
defm : VPatVFNRCLIP<"vfnrclip_x_f_qf", "VFNRCLIP_X_F_QF">;
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}
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let Predicates = [HasVendorXSiFivecdiscarddlone] in {
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let hasNoSchedulingInfo = 1, hasSideEffects = 1, mayLoad = 0, mayStore = 0,
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DecoderNamespace = "XSiFivecdiscarddlone" in
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def SF_CDISCARD_D_L1
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: RVInstIUnary<0b111111000010, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1),
817+
"sf.cdiscard.d.l1", "$rs1">, Sched<[]> {
818+
let rd = 0;
819+
}
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def : InstAlias<"sf.cdiscard.d.l1", (SF_CDISCARD_D_L1 X0)>;
821+
} // Predicates = [HasVendorXSifivecdiscarddlone]
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823+
let Predicates = [HasVendorXSiFivecflushdlone] in {
824+
let hasNoSchedulingInfo = 1, hasSideEffects = 1, mayLoad = 0, mayStore = 0,
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DecoderNamespace = "XSiFivecflushdlone" in
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def SF_CFLUSH_D_L1
827+
: RVInstIUnary<0b111111000000, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1),
828+
"sf.cflush.d.l1", "$rs1">, Sched<[]> {
829+
let rd = 0;
830+
}
831+
def : InstAlias<"sf.cflush.d.l1", (SF_CFLUSH_D_L1 X0)>;
832+
} // Predicates = [HasVendorXSifivecflushdlone]
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834+
let Predicates = [HasVendorXSfcease] in {
835+
let hasNoSchedulingInfo = 1, hasSideEffects = 1, mayLoad = 0, mayStore = 0,
836+
DecoderNamespace = "XSfcease" in
837+
def SF_CEASE : RVInstIUnary<0b001100000101, 0b000, OPC_SYSTEM, (outs), (ins),
838+
"sf.cease", "">, Sched<[]> {
839+
let rs1 = 0b00000;
840+
let rd = 0b00000;
841+
}
842+
}

‎llvm/test/MC/RISCV/xsifive-invalid.s‎

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@@ -0,0 +1,20 @@
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# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -triple riscv64 < %s 2>&1 | FileCheck %s
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sf.cflush.d.l1 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
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sf.cdiscard.d.l1 0x10 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
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sf.cflush.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction){{$}}
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sf.cflush.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction){{$}}
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sf.cdiscard.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction){{$}}
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sf.cdiscard.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction){{$}}
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sf.cease x1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
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sf.cease 0x10 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
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sf.cease # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcease' (SiFive sf.cease Instruction){{$}}

‎llvm/test/MC/RISCV/xsifive-valid.s‎

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@@ -0,0 +1,36 @@
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# RUN: llvm-mc %s -triple=riscv32 -mattr=+xsifivecdiscarddlone,+xsifivecflushdlone,+xsfcease -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
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# RUN: llvm-mc %s -triple=riscv64 -mattr=+xsifivecdiscarddlone,+xsifivecflushdlone,+xsfcease -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xsifivecdiscarddlone,+xsifivecflushdlone,+xsfcease < %s \
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# RUN: | llvm-objdump --mattr=+xsifivecdiscarddlone,+xsifivecflushdlone,+xsfcease -M no-aliases -d - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
8+
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xsifivecdiscarddlone,+xsifivecflushdlone,+xsfcease < %s \
9+
# RUN: | llvm-objdump --mattr=+xsifivecdiscarddlone,+xsifivecflushdlone,+xsfcease -M no-aliases -d - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
11+
12+
# CHECK-INST: sf.cflush.d.l1 zero
13+
# CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc]
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sf.cflush.d.l1 x0
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# CHECK-INST: sf.cflush.d.l1 zero
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# CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc]
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sf.cflush.d.l1
18+
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# CHECK-INST: sf.cflush.d.l1 t2
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# CHECK-ENC: encoding: [0x73,0x80,0x03,0xfc]
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sf.cflush.d.l1 x7
22+
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# CHECK-INST: sf.cdiscard.d.l1 zero
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# CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc]
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sf.cdiscard.d.l1 x0
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# CHECK-INST: sf.cdiscard.d.l1 zero
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# CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc]
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sf.cdiscard.d.l1
29+
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# CHECK-INST: sf.cdiscard.d.l1 t2
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# CHECK-ENC: encoding: [0x73,0x80,0x23,0xfc]
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sf.cdiscard.d.l1 x7
33+
34+
# CHECK-INST: sf.cease
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# CHECK-ENC: encoding: [0x73,0x00,0x50,0x30]
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sf.cease

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