Skip to content

Commit 20b3ab5

Browse files
MaskRayMaskRay
committed
MCFixup: Remove unused Loc argument
MCFixup::Loc has been removed in favor of MCExpr::Loc through `const MCExpr *Value` (commit 777391a).
1 parent 777391a commit 20b3ab5

File tree

17 files changed

+79
-86
lines changed

17 files changed

+79
-86
lines changed

‎llvm/include/llvm/MC/MCFixup.h‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -90,9 +90,8 @@ class MCFixup {
9090
FI.Kind = Kind;
9191
return FI;
9292
}
93-
static MCFixup create(uint32_t Offset, const MCExpr *Value, unsigned Kind,
94-
SMLoc Loc = SMLoc()) {
95-
return create(Offset, Value, MCFixupKind(Kind), Loc);
93+
static MCFixup create(uint32_t Offset, const MCExpr *Value, unsigned Kind) {
94+
return create(Offset, Value, MCFixupKind(Kind));
9695
}
9796

9897
MCFixupKind getKind() const { return Kind; }

‎llvm/lib/MC/MCObjectStreamer.cpp‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -188,7 +188,7 @@ void MCObjectStreamer::emitValueImpl(const MCExpr *Value, unsigned Size,
188188
return;
189189
}
190190
DF->addFixup(MCFixup::create(DF->getContents().size(), Value,
191-
MCFixup::getDataKindForSize(Size), Loc));
191+
MCFixup::getDataKindForSize(Size)));
192192
DF->appendContents(Size, 0);
193193
}
194194

@@ -696,7 +696,7 @@ MCObjectStreamer::emitRelocDirective(const MCExpr &Offset, StringRef Name,
696696
if (OffsetVal.isAbsolute()) {
697697
if (OffsetVal.getConstant() < 0)
698698
return std::make_pair(false, std::string(".reloc offset is negative"));
699-
DF->addFixup(MCFixup::create(OffsetVal.getConstant(), Expr, Kind, Loc));
699+
DF->addFixup(MCFixup::create(OffsetVal.getConstant(), Expr, Kind));
700700
return std::nullopt;
701701
}
702702
if (OffsetVal.getSubSym())
@@ -712,13 +712,13 @@ MCObjectStreamer::emitRelocDirective(const MCExpr &Offset, StringRef Name,
712712
if (Error != std::nullopt)
713713
return Error;
714714

715-
DF->addFixup(MCFixup::create(SymbolOffset + OffsetVal.getConstant(), Expr,
716-
Kind, Loc));
715+
DF->addFixup(
716+
MCFixup::create(SymbolOffset + OffsetVal.getConstant(), Expr, Kind));
717717
return std::nullopt;
718718
}
719719

720720
PendingFixups.emplace_back(
721-
&Symbol, DF, MCFixup::create(OffsetVal.getConstant(), Expr, Kind, Loc));
721+
&Symbol, DF, MCFixup::create(OffsetVal.getConstant(), Expr, Kind));
722722
return std::nullopt;
723723
}
724724

‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -248,7 +248,7 @@ AArch64MCCodeEmitter::getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
248248
else {
249249
assert(MO.isExpr() && "unable to encode load/store imm operand");
250250
MCFixupKind Kind = MCFixupKind(FixupKind);
251-
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
251+
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
252252
++MCNumFixups;
253253
}
254254

@@ -272,7 +272,7 @@ AArch64MCCodeEmitter::getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
272272
MCFixupKind Kind = MI.getOpcode() == AArch64::ADR
273273
? MCFixupKind(AArch64::fixup_aarch64_pcrel_adr_imm21)
274274
: MCFixupKind(AArch64::fixup_aarch64_pcrel_adrp_imm21);
275-
Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
275+
Fixups.push_back(MCFixup::create(0, Expr, Kind));
276276

277277
MCNumFixups += 1;
278278

@@ -302,7 +302,7 @@ AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
302302

303303
// Encode the 12 bits of the fixup.
304304
MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_add_imm12);
305-
Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
305+
Fixups.push_back(MCFixup::create(0, Expr, Kind));
306306

307307
++MCNumFixups;
308308

@@ -330,7 +330,7 @@ uint32_t AArch64MCCodeEmitter::getCondBranchTargetOpValue(
330330
assert(MO.isExpr() && "Unexpected target type!");
331331

332332
MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_pcrel_branch19);
333-
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
333+
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
334334

335335
++MCNumFixups;
336336

@@ -351,7 +351,7 @@ uint32_t AArch64MCCodeEmitter::getCondCompBranchTargetOpValue(
351351
assert(MO.isExpr() && "Unexpected target type!");
352352

353353
MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_pcrel_branch9);
354-
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
354+
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
355355

356356
++MCNumFixups;
357357

@@ -374,7 +374,7 @@ AArch64MCCodeEmitter::getPAuthPCRelOpValue(const MCInst &MI, unsigned OpIdx,
374374
assert(MO.isExpr() && "Unexpected target type!");
375375

376376
MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_pcrel_branch16);
377-
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
377+
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
378378

379379
++MCNumFixups;
380380

@@ -396,7 +396,7 @@ AArch64MCCodeEmitter::getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
396396
assert(MO.isExpr() && "Unexpected target type!");
397397

398398
MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_ldr_pcrel_imm19);
399-
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
399+
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
400400

401401
++MCNumFixups;
402402

@@ -423,8 +423,8 @@ AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
423423
return MO.getImm();
424424
assert(MO.isExpr() && "Unexpected movz/movk immediate");
425425

426-
Fixups.push_back(MCFixup::create(
427-
0, MO.getExpr(), MCFixupKind(AArch64::fixup_aarch64_movw), MI.getLoc()));
426+
Fixups.push_back(MCFixup::create(0, MO.getExpr(),
427+
MCFixupKind(AArch64::fixup_aarch64_movw)));
428428

429429
++MCNumFixups;
430430

@@ -444,7 +444,7 @@ uint32_t AArch64MCCodeEmitter::getTestBranchTargetOpValue(
444444
assert(MO.isExpr() && "Unexpected ADR target type!");
445445

446446
MCFixupKind Kind = MCFixupKind(AArch64::fixup_aarch64_pcrel_branch14);
447-
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
447+
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
448448

449449
++MCNumFixups;
450450

@@ -468,7 +468,7 @@ AArch64MCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
468468
MCFixupKind Kind = MI.getOpcode() == AArch64::BL
469469
? MCFixupKind(AArch64::fixup_aarch64_pcrel_call26)
470470
: MCFixupKind(AArch64::fixup_aarch64_pcrel_branch26);
471-
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
471+
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
472472

473473
++MCNumFixups;
474474

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -446,7 +446,7 @@ void AMDGPUMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
446446
if (MO.isExpr()) {
447447
const MCExpr *Expr = MO.getExpr();
448448
MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br;
449-
Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
449+
Fixups.push_back(MCFixup::create(0, Expr, Kind));
450450
Op = APInt::getZero(96);
451451
} else {
452452
getMachineOpValue(MI, MO, Op, Fixups, STI);
@@ -662,7 +662,7 @@ void AMDGPUMCCodeEmitter::getMachineOpValueCommon(
662662
uint32_t Offset = Desc.getSize();
663663
assert(Offset == 4 || Offset == 8);
664664

665-
Fixups.push_back(MCFixup::create(Offset, MO.getExpr(), Kind, MI.getLoc()));
665+
Fixups.push_back(MCFixup::create(Offset, MO.getExpr(), Kind));
666666
}
667667

668668
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());

‎llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -166,7 +166,7 @@ uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
166166
// We can't easily get the order of the current one, so compare against
167167
// the first one and adjust offset.
168168
const unsigned offset = (&MO == &MI.getOperand(0)) ? 0 : 4;
169-
Fixups.push_back(MCFixup::create(offset, MO.getExpr(), FK_SecRel_4, MI.getLoc()));
169+
Fixups.push_back(MCFixup::create(offset, MO.getExpr(), FK_SecRel_4));
170170
return 0;
171171
}
172172

‎llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -321,7 +321,7 @@ class ARMMCCodeEmitter : public MCCodeEmitter {
321321
const MCExpr *Expr = MO.getExpr();
322322
// Fixups resolve to plain values that need to be encoded.
323323
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_mod_imm);
324-
Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
324+
Fixups.push_back(MCFixup::create(0, Expr, Kind));
325325
return 0;
326326
}
327327

@@ -340,7 +340,7 @@ class ARMMCCodeEmitter : public MCCodeEmitter {
340340
const MCExpr *Expr = MO.getExpr();
341341
// Fixups resolve to plain values that need to be encoded.
342342
MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_so_imm);
343-
Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
343+
Fixups.push_back(MCFixup::create(0, Expr, Kind));
344344
return 0;
345345
}
346346
unsigned SoImm = MO.getImm();
@@ -616,7 +616,7 @@ static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
616616
assert(MO.isExpr() && "Unexpected branch target type!");
617617
const MCExpr *Expr = MO.getExpr();
618618
MCFixupKind Kind = MCFixupKind(FixupKind);
619-
Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
619+
Fixups.push_back(MCFixup::create(0, Expr, Kind));
620620

621621
// All of the information is in the fixup.
622622
return 0;
@@ -979,7 +979,7 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
979979
Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
980980
isAdd = false; // 'U' bit is set as part of the fixup.
981981
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_ldst_abs_12);
982-
Fixups.push_back(MCFixup::create(0, MO1.getExpr(), Kind, MI.getLoc()));
982+
Fixups.push_back(MCFixup::create(0, MO1.getExpr(), Kind));
983983
}
984984
} else if (MO.isExpr()) {
985985
Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
@@ -989,7 +989,7 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
989989
Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
990990
else
991991
Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
992-
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
992+
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
993993

994994
++MCNumCPRelocations;
995995
} else {
@@ -1114,7 +1114,7 @@ getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
11141114
assert(MO.isExpr() && "Unexpected machine operand type!");
11151115
const MCExpr *Expr = MO.getExpr();
11161116
MCFixupKind Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
1117-
Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1117+
Fixups.push_back(MCFixup::create(0, Expr, Kind));
11181118

11191119
++MCNumCPRelocations;
11201120
} else
@@ -1251,7 +1251,7 @@ uint32_t ARMMCCodeEmitter::getHiLoImmOpValue(const MCInst &MI, unsigned OpIdx,
12511251
break;
12521252
}
12531253

1254-
Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc()));
1254+
Fixups.push_back(MCFixup::create(0, E, Kind));
12551255
return 0;
12561256
}
12571257
// If the expression doesn't have :upper16:, :lower16: on it, it's just a
@@ -1373,7 +1373,7 @@ getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
13731373
assert(MO.isExpr() && "Unexpected machine operand type!");
13741374
const MCExpr *Expr = MO.getExpr();
13751375
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10_unscaled);
1376-
Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1376+
Fixups.push_back(MCFixup::create(0, Expr, Kind));
13771377

13781378
++MCNumCPRelocations;
13791379
return (Rn << 9) | (1 << 13);
@@ -1455,7 +1455,7 @@ getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
14551455
Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
14561456
else
14571457
Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1458-
Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1458+
Fixups.push_back(MCFixup::create(0, Expr, Kind));
14591459

14601460
++MCNumCPRelocations;
14611461
} else {
@@ -1495,7 +1495,7 @@ getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
14951495
Kind = MCFixupKind(ARM::fixup_t2_pcrel_9);
14961496
else
14971497
Kind = MCFixupKind(ARM::fixup_arm_pcrel_9);
1498-
Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1498+
Fixups.push_back(MCFixup::create(0, Expr, Kind));
14991499

15001500
++MCNumCPRelocations;
15011501
} else {
@@ -1950,7 +1950,7 @@ ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
19501950
const MCExpr *DiffExpr = MCBinaryExpr::createSub(
19511951
MO.getExpr(), BranchMO.getExpr(), CTX);
19521952
MCFixupKind Kind = MCFixupKind(ARM::fixup_bfcsel_else_target);
1953-
Fixups.push_back(llvm::MCFixup::create(0, DiffExpr, Kind, MI.getLoc()));
1953+
Fixups.push_back(llvm::MCFixup::create(0, DiffExpr, Kind));
19541954
return 0;
19551955
}
19561956

‎llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp‎

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -110,8 +110,7 @@ AVRMCCodeEmitter::encodeRelCondBrTarget(const MCInst &MI, unsigned OpNo,
110110
const MCOperand &MO = MI.getOperand(OpNo);
111111

112112
if (MO.isExpr()) {
113-
Fixups.push_back(
114-
MCFixup::create(0, MO.getExpr(), MCFixupKind(Fixup), MI.getLoc()));
113+
Fixups.push_back(MCFixup::create(0, MO.getExpr(), MCFixupKind(Fixup)));
115114
return 0;
116115
}
117116

@@ -156,8 +155,8 @@ unsigned AVRMCCodeEmitter::encodeMemri(const MCInst &MI, unsigned OpNo,
156155
OffsetBits = OffsetOp.getImm();
157156
} else if (OffsetOp.isExpr()) {
158157
OffsetBits = 0;
159-
Fixups.push_back(MCFixup::create(0, OffsetOp.getExpr(),
160-
MCFixupKind(AVR::fixup_6), MI.getLoc()));
158+
Fixups.push_back(
159+
MCFixup::create(0, OffsetOp.getExpr(), MCFixupKind(AVR::fixup_6)));
161160
} else {
162161
llvm_unreachable("Invalid value for offset");
163162
}
@@ -191,8 +190,7 @@ unsigned AVRMCCodeEmitter::encodeImm(const MCInst &MI, unsigned OpNo,
191190
}
192191

193192
MCFixupKind FixupKind = static_cast<MCFixupKind>(Fixup);
194-
Fixups.push_back(
195-
MCFixup::create(Offset, MO.getExpr(), FixupKind, MI.getLoc()));
193+
Fixups.push_back(MCFixup::create(Offset, MO.getExpr(), FixupKind));
196194

197195
return 0;
198196
}
@@ -208,7 +206,7 @@ unsigned AVRMCCodeEmitter::encodeCallTarget(const MCInst &MI, unsigned OpNo,
208206

209207
if (MO.isExpr()) {
210208
MCFixupKind FixupKind = static_cast<MCFixupKind>(AVR::fixup_call);
211-
Fixups.push_back(MCFixup::create(0, MO.getExpr(), FixupKind, MI.getLoc()));
209+
Fixups.push_back(MCFixup::create(0, MO.getExpr(), FixupKind));
212210
return 0;
213211
}
214212

‎llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.h‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ class CSKYMCCodeEmitter : public MCCodeEmitter {
5757
assert(MO.isExpr() && "Unexpected MO type.");
5858

5959
MCFixupKind Kind = getTargetFixup(MO.getExpr());
60-
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
60+
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
6161
return 0;
6262
}
6363

@@ -110,7 +110,7 @@ class CSKYMCCodeEmitter : public MCCodeEmitter {
110110
if (MO.getExpr()->getKind() == MCExpr::Specifier)
111111
Kind = getTargetFixup(MO.getExpr());
112112

113-
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
113+
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
114114
return 0;
115115
}
116116

@@ -125,7 +125,7 @@ class CSKYMCCodeEmitter : public MCCodeEmitter {
125125
if (MO.getExpr()->getKind() == MCExpr::Specifier)
126126
Kind = getTargetFixup(MO.getExpr());
127127

128-
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
128+
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
129129
return 0;
130130
}
131131

@@ -140,7 +140,7 @@ class CSKYMCCodeEmitter : public MCCodeEmitter {
140140
if (MO.getExpr()->getKind() == MCExpr::Specifier)
141141
Kind = getTargetFixup(MO.getExpr());
142142

143-
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
143+
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
144144
return 0;
145145
}
146146

@@ -154,7 +154,7 @@ class CSKYMCCodeEmitter : public MCCodeEmitter {
154154
if (MO.getExpr()->getKind() == MCExpr::Specifier)
155155
Kind = getTargetFixup(MO.getExpr());
156156

157-
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
157+
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
158158
return 0;
159159
}
160160

@@ -168,7 +168,7 @@ class CSKYMCCodeEmitter : public MCCodeEmitter {
168168
if (MO.getExpr()->getKind() == MCExpr::Specifier)
169169
Kind = getTargetFixup(MO.getExpr());
170170

171-
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
171+
Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind));
172172
return 0;
173173
}
174174

‎llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -698,8 +698,8 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
698698
FixupExpr = MCBinaryExpr::createAdd(FixupExpr, C, MCT);
699699
}
700700

701-
MCFixup Fixup = MCFixup::create(State.Addend, FixupExpr,
702-
MCFixupKind(FixupKind), MI.getLoc());
701+
MCFixup Fixup =
702+
MCFixup::create(State.Addend, FixupExpr, MCFixupKind(FixupKind));
703703
Fixups.push_back(Fixup);
704704
// All of the information is in the fixup.
705705
return 0;

‎llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -195,8 +195,7 @@ LoongArchMCCodeEmitter::getExprOpValue(const MCInst &MI, const MCOperand &MO,
195195
assert(FixupKind != LoongArch::fixup_loongarch_invalid &&
196196
"Unhandled expression!");
197197

198-
Fixups.push_back(
199-
MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
198+
Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
200199
// If linker relaxation is enabled and supported by this relocation, set
201200
// a bit so that if fixup is unresolved, a R_LARCH_RELAX relocation will be
202201
// appended.
@@ -249,8 +248,7 @@ void LoongArchMCCodeEmitter::expandAddTPRel(const MCInst &MI,
249248
"Expected %le_add_r relocation on TP-relative symbol");
250249

251250
// Emit the correct %le_add_r relocation for the symbol.
252-
Fixups.push_back(
253-
MCFixup::create(0, Expr, ELF::R_LARCH_TLS_LE_ADD_R, MI.getLoc()));
251+
Fixups.push_back(MCFixup::create(0, Expr, ELF::R_LARCH_TLS_LE_ADD_R));
254252
if (STI.hasFeature(LoongArch::FeatureRelax))
255253
Fixups.back().setLinkerRelaxable();
256254

0 commit comments

Comments
 (0)